The present invention makes possible to generate pulses having set period in high speed. An address series from a pattern generator 11 is converted into two address series, each having two time enabling periods by conversion means 40. A period value memory is read out by these two series of address series. A first and a second fractions read out are stored in flip-flops (FF hereinafter) 41.sub.1 and 41.sub.2 respectively, and integers are stored in FF 43.sub.1 and 43.sub.2 respectively. The output of the FF 41.sub.2 is stored in a FF 46.sub.2. The outputs of the FFs 41.sub.1 and 41.sub.2 are summed and accumulated in an adder 45.sub.1 and the outputs of the FFs 41.sub.1 and 46.sub.2 are summed and accumulated in an adder 45.sub.2. The outputs of the FFs 43.sub.1 and 43.sub.2 are set in coincidence detection counters 62.sub.1 and 62.sub.2 via FFs 58.sub.1 and 58.sub.2 respectively. Each of the counters 62.sub.1 and 62.sub.2 counts the clock and then outputs a signal when the count value coincides with the set value. The output signals are supplied to delay circuits 64.sub.1 and 64.sub.2 respectively. If a carry output from each of the adders 45.sub.1 and 45.sub.2 exists, each of the respective outputs from the delay circuits is delayed by one clock, and if a carry output does not exist, each of the respective outputs is outputted without delay.