公开(公告)号：US07461314B2

公开(公告)日：2008-12-02

申请号：US11124477

申请日：2005-05-06

申请人： Noriaki Chiba ,  Yasutaka Tsuruki

发明人： Noriaki Chiba ,  Yasutaka Tsuruki

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31924 ,  G01R31/31922 ,  G01R31/31928

摘要： A test device includes: the first reference clock generation unit for generating the first reference clock; the first test rate generation unit for generating the first test rate clock based on the first reference clock; the first driver unit for supplying the first test pattern to an electronic device based on the first test rate clock; the second reference clock generation unit for generating the second reference clock; the first phase synchronization unit for synchronizing the phase of the second reference clock with the phase of the first test rate clock; the second test rate generation unit for generating the second test rate clock based on the second reference clock having the synchronized phase; and the second driver unit for supplying the second test pattern to the electronic device based on the second test rate clock.

摘要翻译： 测试装置包括：第一参考时钟产生单元，用于产生第一参考时钟; 第一测试率生成单元，用于基于第一参考时钟产生第一测试速率时钟; 所述第一驱动器单元，用于基于所述第一测试速率时钟向所述电子设备提供所述第一测试图案; 所述第二参考时钟生成单元用于产生所述第二参考时钟; 第一相位同步单元，用于使第二参考时钟的相位与第一测试速率时钟的相位同步; 第二测试率生成单元，用于基于具有同步相位的第二参考时钟产生第二测试速率时钟; 以及第二驱动器单元，用于基于第二测试速率时钟将第二测试图案提供给电子设备。

公开(公告)号：US5886536A

公开(公告)日：1999-03-23

申请号：US793129

申请日：1997-04-25

申请人： Yasutaka Tsuruki

发明人： Yasutaka Tsuruki

IPC分类号： G01R31/317 ,  G01R31/319 ,  H03L7/06 ,  G01R23/02

CPC分类号： G01R31/31709 ,  G01R31/31922 ,  H03L7/06

摘要： The present invention aims to take in an external clock signal generated by a device under test into a semiconductor tester and eliminate jitters involved in the clock signal, thereby stabilizes the clock signal, and to use the clock signal as an operation clock of the tester. Hence, a divider A11 which takes the clock signal 21 generated by the device under test as an input, a phase detector circuit 12, a loop filter 13, a VCO 14 and a divider B16 are provided. In addition, the invention includes a test rate generator 15 and an inter-leave circuit 18. The operation clock which is an output of the VCO 14 is input to the test rate generator 15 to output a test rate signal 23, and distributes the test rate signal to the inside circuits as well as feeds back to the phase detector 12 through the divider B16.

摘要翻译： PCT No.PCT / JP95 / 01438 Sec。 371日期1997年04月25日 102（e）日期1997年4月25日PCT提交1995年7月20日PCT公布。 出版物WO97 / 04327 日期：1997年2月6日本发明旨在将由被测器件产生的外部时钟信号置入半导体测试器中，消除涉及时钟信号的抖动，从而稳定时钟信号，并将时钟信号用作操作 测试仪的时钟。 因此，提供了将由被测器件产生的时钟信号21作为输入的分频器A11，相位检测器电路12，环路滤波器13，VCO 14和分频器B16。 此外，本发明包括测试速率发生器15和间歇电路18.作为VCO14的输出的操作时钟被输入到测试速率发生器15以输出测试速率信号23，并且分配测试 速率信号到内部电路，并且通过分频器B16反馈到相位检测器12。

公开(公告)号：US20050210341A1

公开(公告)日：2005-09-22

申请号：US11124477

申请日：2005-05-06

申请人： Noriaki Chiba ,  Yasutaka Tsuruki

发明人： Noriaki Chiba ,  Yasutaka Tsuruki

IPC分类号： G01R31/28 ,  G01R31/319 ,  G06F11/00

CPC分类号： G01R31/31924 ,  G01R31/31922 ,  G01R31/31928

摘要： A test device includes: the first reference clock generation unit for generating the first reference clock; the first test rate generation unit for generating the first test rate clock based on the first reference clock; the first driver unit for supplying the first test pattern to an electronic device based on the first test rate clock; the second reference clock generation unit for generating the second reference clock; the first phase synchronization unit for synchronizing the phase of the second reference clock with the phase of the first test rate clock; the second test rate generation unit for generating the second test rate clock based on the second reference clock having the synchronized phase; and the second driver unit for supplying the second test pattern to the electronic device based on the second test rate clock.

摘要翻译： 测试装置包括：第一参考时钟产生单元，用于产生第一参考时钟; 第一测试率生成单元，用于基于第一参考时钟产生第一测试速率时钟; 所述第一驱动器单元，用于基于所述第一测试速率时钟向所述电子设备提供所述第一测试图案; 所述第二参考时钟生成单元用于产生所述第二参考时钟; 第一相位同步单元，用于使第二参考时钟的相位与第一测试速率时钟的相位同步; 第二测试率生成单元，用于基于具有同步相位的第二参考时钟产生第二测试速率时钟; 以及第二驱动器单元，用于基于第二测试速率时钟将第二测试图案提供给电子设备。

公开(公告)号：US5761100A

公开(公告)日：1998-06-02

申请号：US750507

申请日：1996-12-11

申请人： Masayuki Itoh ,  Yasutaka Tsuruki

发明人： Masayuki Itoh ,  Yasutaka Tsuruki

IPC分类号： G01R31/3183 ,  G01R31/319 ,  G06F1/02

CPC分类号： G01R31/31922

摘要： The present invention makes possible to generate pulses having set period in high speed. An address series from a pattern generator 11 is converted into two address series, each having two time enabling periods by conversion means 40. A period value memory is read out by these two series of address series. A first and a second fractions read out are stored in flip-flops (FF hereinafter) 41.sub.1 and 41.sub.2 respectively, and integers are stored in FF 43.sub.1 and 43.sub.2 respectively. The output of the FF 41.sub.2 is stored in a FF 46.sub.2. The outputs of the FFs 41.sub.1 and 41.sub.2 are summed and accumulated in an adder 45.sub.1 and the outputs of the FFs 41.sub.1 and 46.sub.2 are summed and accumulated in an adder 45.sub.2. The outputs of the FFs 43.sub.1 and 43.sub.2 are set in coincidence detection counters 62.sub.1 and 62.sub.2 via FFs 58.sub.1 and 58.sub.2 respectively. Each of the counters 62.sub.1 and 62.sub.2 counts the clock and then outputs a signal when the count value coincides with the set value. The output signals are supplied to delay circuits 64.sub.1 and 64.sub.2 respectively. If a carry output from each of the adders 45.sub.1 and 45.sub.2 exists, each of the respective outputs from the delay circuits is delayed by one clock, and if a carry output does not exist, each of the respective outputs is outputted without delay.

摘要翻译： PCT No.PCT / JP95 / 00722 Sec。 371日期1996年12月11日第 102（e）日期1996年12月11日PCT提交1995年4月13日PCT公布。 公开号WO96 / 32654 日期：1996年10月17日本发明可以产生高速设定周期的脉冲。 来自图案生成器11的地址序列被转换为两个地址序列，每个地址序列由转换装置40具有两个时间允许周期。通过这两个地址序列读出周期值存储器。 读出的第一和第二分数分别存储在触发器（FF）411和412中，整数分别存储在FF 431和432中。 FF 412的输出存储在FF462中。将FF411和412的输出相加并累加在加法器451中，并将FF411和462的输出相加并累加在加法器452中。输出 FF 431和432分别经由FF 581和582设置在重合检测计数器621和622中。 每个计数器621和622对时钟进行计数，然后当计数值与设定值一致时输出信号。 输出信号分别提供给延迟电路641和642。 如果存在来自加法器451和452中的每一个的进位输出，则来自延迟电路的各个输出中的每一个被延迟一个时钟，并且如果不存在进位输出，则各个输出中的每一个输出无延迟。

公开(公告)号：US06956395B2

公开(公告)日：2005-10-18

申请号：US10889379

申请日：2004-07-12

申请人： Hideyuki Oshima ,  Yasutaka Tsuruki

发明人： Hideyuki Oshima ,  Yasutaka Tsuruki

IPC分类号： G01R31/319 ,  G01R31/26 ,  G01R31/28

CPC分类号： G01R31/31922 ,  G01R31/31928

摘要： A tester comprising a reference clock generating section for generating a reference clock having a first frequency, a first test rate generating section for generating a first test rate clock having a frequency which is about an integral multiple of the first frequency, a second test rate generating section for generating a second test rate clock having a frequency which is about an integral multiple of the first frequency and different from the frequency of the first test rate clock, a first driver section for supplying a test pattern to an electronic device according to the first test rate clock, and a second deriver section for supplying the test pattern to the electronic device according to the second test rate clock.

摘要翻译： 一种测试器，包括用于产生具有第一频率的参考时钟的参考时钟产生部分，用于产生具有大约是第一频率的整数倍的频率的第一测试速率时钟的第一测试速率产生部分，产生第二频率的第二测试速率 用于产生具有大约是第一频率的整数倍并且不同于第一测试速率时钟的频率的频率的第二测试速率时钟的第一测试速率时钟;第一驱动器部分，用于将测试图案提供给根据第一测试时钟的电子设备 测试速率时钟，以及第二提升部分，用于根据第二测试速率时钟将测试图案提供给电子设备。

公开(公告)号：US07187192B2

公开(公告)日：2007-03-06

申请号：US10512296

申请日：2003-04-21

申请人： Hideyuki Oshima ,  Yasutaka Tsuruki

发明人： Hideyuki Oshima ,  Yasutaka Tsuruki

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/02

CPC分类号： G01R31/31922

摘要： A semiconductor test device for acquiring a multiplexed clock signal from LSI output data and using the clock to test the LSI. The device includes a time interpolator and registers connected in series. The time interpolator has flip-flops connected in parallel for receiving output data from an LSI under test, a delay circuit for successively inputting strobes delayed at a constant timing interval to the flip-flops and outputting time-series level data, and an encoder for receiving the time-series level data from the flip-flops and encoding it into position data indicating an edge timing. The registers successively store position data from the encoder and output them at a predetermined timing. The device further includes a digital filter for outputting the position data from the registers as a recovery clock.

摘要翻译： 一种用于从LSI输出数据获取多路复用时钟信号并使用时钟测试LSI的半导体测试装置。 该装置包括时间插值器和串联连接的寄存器。 时间插值器具有并联连接的触发器，用于接收来自被测LSI的输出数据，用于连续输入以恒定定时间隔延迟的选通脉冲并延迟触发器并输出时间序列电平数据的延迟电路，以及编码器 从触发器接收时间序列电平数据并将其编码成表示边沿定时的位置数据。 寄存器依次存储来自编码器的位置数据，并在预定的时刻输出。 该装置还包括用于从作为恢复时钟的寄存器输出位置数据的数字滤波器。

公开(公告)号：US06791389B2

公开(公告)日：2004-09-14

申请号：US10306129

申请日：2002-11-27

申请人： Hiroyuki Mikami ,  Yasutaka Tsuruki

发明人： Hiroyuki Mikami ,  Yasutaka Tsuruki

IPC分类号： H03H1126

CPC分类号： G01R31/31937 ,  H03K5/133

摘要： According to the present invention, a variable delay circuit includes a delay circuit unit group, a control unit and an offset delay amount memory group. The delay circuit unit group includes a plurality of delay circuit units, and the plurality of delay circuit units includes two paths having different delay amounts. The offset delay amount memory group includes a plurality of offset delay amount memories, and offset delay amounts corresponding to delay amounts of the first paths of the corresponding delay circuit units are set in the plurality of offset delay amount memories. The control unit includes a plurality of subtracting units, and the plurality of subtracting units select paths of the delay circuit units through which an input signal may pass by using a delay setting value and offset delay amounts. It is possible to reduce volume of the circuit and remove a table since the path is selected by calculation.

摘要翻译： 根据本发明，可变延迟电路包括延迟电路单元组，控制单元和偏移延迟量存储器组。 延迟电路单元组包括多个延迟电路单元，并且多个延迟电路单元包括具有不同延迟量的两个路径。 偏移延迟量存储组包括多个偏移延迟量存储器，并且在多个偏移延迟量存储器中设置与对应的延迟电路单元的第一路径的延迟量对应的偏移延迟量。 控制单元包括多个减法单元，并且多个减法单元通过使用延迟设定值和偏移延迟量来选择输入信号可以通过的延迟电路单元的路径。 由于通过计算选择了路径，所以可以减小电路的体积并删除一个表。

公开(公告)号：US06768360B2

公开(公告)日：2004-07-27

申请号：US09948503

申请日：2001-09-06

申请人： Yasutaka Tsuruki

发明人： Yasutaka Tsuruki

IPC分类号： H03L700

CPC分类号： G01R31/31922

摘要： A timing signal generation circuit comprising: a negative feedback loop comprising; a variable delay circuit for outputting a timing signal delayed from an input clock signal by a delay amount designated by a delay code; a phase difference detector for detecting a phase difference between the timing signal and the input clock signal to output a detection signal; and a loop filter for smoothing a waveform of the detection signal to generate a voltage signal and for feeding the voltage signal back to the variable delay circuit: and a cancel unit for generating a reverse detection signal based on the delay code to cancel the phase difference caused by a change in the delay amount where the reverse detection signal is supplied to the low pass filter.

摘要翻译： 一种定时信号产生电路，包括：负反馈回路，包括： 一个可变延迟电路，用于将由延迟码指定的延迟量从输入时钟信号延迟的定时信号输出; 相位差检测器，用于检测定时信号和输入时钟信号之间的相位差，以输出检测信号; 以及环路滤波器，用于平滑检测信号的波形以产生电压信号并将电压信号馈送回可变延迟电路;以及消除单元，用于基于延迟码产生反向检测信号以消除相位差 由反向检测信号提供给低通滤波器的延迟量的变化引起的。