In a matrix array of memory cells, each memory cell includes a control gate, and first and second terminals for defining a channel therebetween, with the second terminals of the memory cells being connected to a common circuit node. During a write modes a row of memory cells and a column of memory cells are selected, and a first voltage is supplied to the control gates of the memory cells of the selected row and a second voltage which varies positively as a function of temperature is supplied to the first terminals of the memory cells of the selected column for trapping electrons in at least one of the memory cells. During an erase mode, ground potential is supplied to the control gates of all memory cells and a third voltage which varies negatively as a function of temperature is supplied to the common circuit node to remove the trapped electrons from the memory cells.