A mixed-modulo address generation unit has several inputs. The unit effectively adds together a subset of these inputs in a reduced modulus while simultaneously adding other inputs in a full modulus to the partial sum of reduced-modulus inputs. The subset of inputs receives reduced-width address components such as 16-bit address components which are effectively added together in modulo 64K. The other inputs receive full-width address components such as 32-bit components which are added in the full modulus, 4G. Reduced-width components are zero-extended to 32 bits before input to a standard 32-bit adder. A 16-bit carry generator also receives the reduced-width components and generates the carries out of the 16th bit position. When one or more carries is detected, a correction term is subtracted from the initial sum which is recirculated to the adder's input in a subsequent step. The correction term is the number of carries out of the 16th bit position multiplied by 64K. The full-width segment bases for all active segments are stored in the register file, but the most commonly accessed segments, the data and stack segments, have a copy of their segment bases also stored in a shadow register for input to the adder. Thus the number of read ports to the register file is reduced by the shadow segment register. Less-frequently-used segments require an additional step through the adder to generate the address, but addresses in the data and stack segments are generated in a single cycle.