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公开(公告)号：US12020026B2
公开(公告)日：2024-06-25
申请号：US17840326
申请日：2022-06-14
发明人： Taixu Tian , Zhongzhen Wang , Jincong Huang , Wenliang Shen , Weijian Luo
CPC分类号： G06F9/24 , G06F9/267 , G06F9/30145
摘要： An instruction writing method, apparatus, and network device are provided to reduce a requirement for a storage space of a microcode processor. The method includes obtaining, by a first device, first indication information, where the first indication information indicates the first device to enable a first service function, and writing, by the first device, a first microcode instruction set corresponding to the first service function into an unused storage space of a target microcode processor in a network processor, where a size of the unused storage space is greater than or equal to a size of the first microcode instruction set.
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公开(公告)号：US11809857B2
公开(公告)日：2023-11-07
申请号：US17692670
申请日：2022-03-11
摘要： A method includes receiving, by a microcontroller, a live firmware update (LFU) command from an external host; and downloading, by the microcontroller, an image of a new version of firmware responsive to the LFU command. During a first time period, the method includes initializing only variables contained in the new version that are not contained in an old version of firmware. During a second time period, the method includes updating one or more of an interrupt vector table, a function pointer, and/or a stack pointer responsive to the new version. The second time period begins responsive to completing initialization of the variables.
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公开(公告)号：US20230305847A1
公开(公告)日：2023-09-28
申请号：US17704131
申请日：2022-03-25
发明人： Pranjal Kumar Dutta
CPC分类号： G06F9/30145 , G06F9/30047 , G06F9/30043 , G06F9/262
摘要： Various example embodiments for supporting a multi-indexed micro-operations cache (MI-UC) in a processor are presented. Various example embodiments for supporting an MI-UC in a processor may be configured to support an MI-UC in which, for a UC line of the MI-UC, multiple indexes into the UC line, for multiple sets of micro-operations (UOPs) stored in the UC line based on decoding of multiple instructions, are supported.
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公开(公告)号：US20230289175A1
公开(公告)日：2023-09-14
申请号：US17692670
申请日：2022-03-11
摘要： A method includes receiving, by a microcontroller, a live firmware update (LFU) command from an external host; and downloading, by the microcontroller, an image of a new version of firmware responsive to the LFU command. During a first time period, the method includes initializing only variables contained in the new version that are not contained in an old version of firmware. During a second time period, the method includes updating one or more of an interrupt vector table, a function pointer, and/or a stack pointer responsive to the new version. The second time period begins responsive to completing initialization of the variables.
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公开(公告)号：US11720363B2
公开(公告)日：2023-08-08
申请号：US17485400
申请日：2021-09-25
申请人： Intel Corporation
CPC分类号： G06F9/30145 , G06F9/268 , G06F9/3017 , G06F12/0246
摘要： An apparatus and method for efficient microcode patching. For example, one embodiment of an apparatus comprises: a package comprising one or more integrated circuit dies, the one or more integrated circuit dies comprising: a plurality of cores; and a security controller coupled to the plurality of cores, a first core of the plurality of cores comprising: a decoder to decode a microcode patching instruction, the microcode patching instruction comprising an operand to be used to identify an address; and execution circuitry to execute the microcode patching instruction, wherein responsive to the microcode patching instruction, the execution circuitry and/or security controller are to: retrieve a microcode patch from a location in memory based on the address, validate the microcode patch, apply the microcode patch to update or replace microcode associated with the one or more integrated circuit dies, and transmit the microcode patch to a persistent storage device; wherein the microcode patch is to be subsequently retrieved from the persistent storage device by one or more external security controllers of one or more external integrated circuit dies, the one or more external security controllers to cause the microcode patch to be applied to update or replace microcode associated with the one or more external integrated circuit dies.
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公开(公告)号：US20230097693A1
公开(公告)日：2023-03-30
申请号：US17485400
申请日：2021-09-25
摘要： An apparatus and method for efficient microcode patching. For example, one embodiment of an apparatus comprises: a package comprising one or more integrated circuit dies, the one or more integrated circuit dies comprising: a plurality of cores; and a security controller coupled to the plurality of cores, a first core of the plurality of cores comprising: a decoder to decode a microcode patching instruction, the microcode patching instruction comprising an operand to be used to identify an address; and execution circuitry to execute the microcode patching instruction, wherein responsive to the microcode patching instruction, the execution circuitry and/or security controller are to: retrieve a microcode patch from a location in memory based on the address, validate the microcode patch, apply the microcode patch to update or replace microcode associated with the one or more integrated circuit dies, and transmit the microcode patch to a persistent storage device; wherein the microcode patch is to be subsequently retrieved from the persistent storage device by one or more external security controllers of one or more external integrated circuit dies, the one or more external security controllers to cause the microcode patch to be applied to update or replace microcode associated with the one or more external integrated circuit dies.
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公开(公告)号：US11450086B2
公开(公告)日：2022-09-20
申请号：US16617967
申请日：2018-06-05
发明人： Han-su Cho , Kyung-hoon Kim , Young-hwan Park , Suk-jin Kim , Hyun-jung Kim , Dong-wook Kwon
摘要： Disclosed is an electronic device and method for controlling same. The electronic device comprises: a memory; and a processor which checks an operation instruction for filtering input data of a neural network for each filter of a main pattern selected from a plurality of filters generated according to learning by the neural network, and stores the checked operation instruction in the memory.
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8.发明授权公开(公告)号：US11385901B2
公开(公告)日：2022-07-12
申请号：US15930728
申请日：2020-05-13
发明人： Matthew van Adelsberg , Rohit Joshi , Siqi Wang
摘要： A system including: at least one processor; and at least one memory having stored thereon computer program code that, when executed by the at least one processor, controls the system to: receive a data model identification and a dataset; in response to determining that the data model does not contain a hierarchical structure, perform expectation propagation on the dataset to approximate the data model with a hierarchical structure; divide the dataset into a plurality of channels; for each of the plurality of channels: divide the data into a plurality of microbatches; process each microbatch of the plurality of microbatches through parallel iterators; and process the output of the parallel iterators through single-instruction multiple-data (SIMD) layers; and asynchronously merge results of the SIMD layers.
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公开(公告)号：US11379378B2
公开(公告)日：2022-07-05
申请号：US16921508
申请日：2020-07-06
申请人： SK hynix Inc.
发明人： Jeen Park
IPC分类号： G06F9/26 , G06F12/1045 , G06F12/06 , G11C7/10
摘要： A memory system includes a plurality of memory dies configured to store data; and a controller coupled with the plurality of memory dies through a plurality of channels, wherein the controller decides whether to perform a pairing operation, by comparing the number of pieces of read data to be outputted to an external device, which are included in a first buffer, with an output count reference value, and wherein, in the case where the number of pieces of read data stored in the first buffer is greater than or equal to the output count reference value, the controller gathers other read requests and logical addresses corresponding thereto in a second buffer, and performs the pairing operation.
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公开(公告)号：US20220206793A1
公开(公告)日：2022-06-30
申请号：US17134154
申请日：2020-12-24
申请人： Intel Corporation
发明人： WING SHEK WONG , VIKASH AGARWAL , CHARLES VITU , MADHURA SARODE
摘要： Systems, methods, and apparatuses relating to a scalable reservation station circuit implementing a single unified speculation state propagation and execution wakeup matrix in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode one or more instructions into a first micro-operation to load data from a data cache, a second micro-operation dependent on the first micro-operation, and a third micro-operation dependent on the second micro-operation; an execution circuit to execute the first micro-operation, the second micro-operation, and the third micro-operation; and a reservation station circuit comprising a load speculation tracker circuit and coupled between the decoder circuit and the execution circuit, the load speculation tracker circuit to, for a reservation station entry of the third micro-operation, track progress of the first micro-operation in the data cache to generate a cancellation indication for the third micro-operation in response to a miss of the data in the data cache for the first micro-operation, wherein the load speculation tracker circuit is to begin to track the progress of the first micro-operation in the data cache in response to a dispatch of the first micro-operation into the data cache.
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