A topology for arranging a plurality of transistors between a signal source and an off-chip receiver, using a single power supply voltage. A pass through NFET has a gate controlled by a network comprised of two transistors arrayed between the power supply voltage and the drain of the NFET, which limits overshoots to the power supply voltage and reduces undershoots. Further reduction of undershoots is accomplished by an additional network of transistors, optimally including a PFET in series with the pass through NFET.