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1.发明申请Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability 有权用于调整字面上升电压的方法和系统，以提高相对于SRAM单元稳定性的产量公开(公告)号：US20120075919A1
公开(公告)日：2012-03-29
申请号：US12892191
申请日：2010-09-28
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译： 在制造的SRAM中设置字线上电压的方法。 在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。 然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。 提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。
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2.发明授权公开(公告)号：US07894291B2
公开(公告)日：2011-02-22
申请号：US11162847
申请日：2005-09-26
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译： 提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。 存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值 消费。 电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。 存储器的存储单元阵列可操作以存储数据。 在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。 这在待机模式期间允许数据保存在存储器中。 在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。 在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。
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3.发明申请公开(公告)号：US20080273373A1
公开(公告)日：2008-11-06
申请号：US12146554
申请日：2008-06-26
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译： 一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点 在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗， 其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。
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4.发明授权Apparatus and method for improved SRAM device performance through double gate topology 有权通过双栅拓扑改善SRAM器件性能的装置和方法公开(公告)号：US07408800B1
公开(公告)日：2008-08-05
申请号：US11743686
申请日：2007-05-03
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译： 一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点 在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗， 其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。
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5.发明授权Method and apparatus for improving cycle time in a quad data rate SRAM device 有权用于改善四倍数据速率SRAM器件中的周期时间的方法和装置公开(公告)号：US06967861B2
公开(公告)日：2005-11-22
申请号：US10708379
申请日：2004-02-27
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G11C8/00 , G11C11/00 , G11C11/413
CPC分类号： G11C11/413
摘要： A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured during a second half of the current clock cycle, said current write address used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during said second half of the current clock cycle.
摘要翻译： 一种用于在存储器存储设备中实现自定时的读写操作的方法。 在一个示例性实施例中，该方法包括在当前时钟周期的前半部分期间捕获读取地址，并开始读取操作，以便将对应于所捕获的读取地址的数据读取到一对位线上。 一旦当前时钟周期开始写入操作，以便一旦来自捕获的读取地址的读取数据被读出放大器放大，就会使写入数据出现在该对位线上，其中写入操作使用先前的写入 在前一个时钟周期捕获的地址。 在当前时钟周期的后半段期间捕获当前写入地址，所述当前写入地址用于在随后的时钟周期期间实现的写入操作，其中当前时钟周期的写入操作被独立于捕获的当前写入地址 在当前时钟周期的后半段。
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公开(公告)号：US06922076B2
公开(公告)日：2005-07-26
申请号：US10604936
申请日：2003-08-27
CPC分类号： H04L25/0298 , H04L25/0278
摘要： In a first aspect, a first method is provided for providing multiple termination values using a plurality of binary termination signals. The first method includes the steps of (1) determining a characteristic impedance of a first port by generating a plurality of binary termination signals; and (2) modifying a characteristic impedance of a second port by manipulating one or more of the plurality of binary termination signals. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种使用多个二进制终止信号来提供多个终止值的第一方法。 第一种方法包括以下步骤：（1）通过产生多个二进制终止信号来确定第一端口的特性阻抗; 和（2）通过操纵多个二进制终止信号中的一个或多个来修改第二端口的特性阻抗。 提供了许多其他方面。
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公开(公告)号：US06897674B2
公开(公告)日：2005-05-24
申请号：US10604186
申请日：2003-06-30
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
CPC分类号： G01R31/3004
摘要： A method of tuning an integrated circuit on an integrated circuit chip including: performing a drain current at saturation measurement of one or more test field effect transistors on the integrated circuit chip; selectively programming fuses of a bank of fuses on the integrated circuit chip based on the drain current at saturation measurement; and tuning an output of the integrated circuit based on a pattern of blown and un-blown fuses in the bank of fuses.
摘要翻译： 一种对集成电路芯片上的集成电路进行调谐的方法，包括：在集成电路芯片上的一个或多个测试场效应晶体管的饱和测量时执行漏极电流; 基于饱和度测量时的漏极电流有选择地对集成电路芯片上的熔丝组进行熔丝; 并根据保险丝库中的熔断和未熔断保险丝的模式调整集成电路的输出。
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公开(公告)号：US5781922A
公开(公告)日：1998-07-14
申请号：US751465
申请日：1996-11-19
CPC分类号： G06F12/1054
摘要： A first level (L1) memory cache is structured on page boundaries, allowing for dynamic allocation of N byte pages based upon program needs. The contents of the cache are accessed by first determining the page location by cache address translation and then indexing directly into the cache. A starting page address tag exists for each page in the cache. If the page address is contained in the current page lookup, the in-line data is directly fetched. Direct fetching without address lookup speeds up the cache access cycle. If the address is not a current page, then the page address lookup occurs to obtain the correct page address block index into the page data macro. If a miss occurs, a page reload follows.
摘要翻译： 第一级（L1）存储器高速缓存在页边界上构成，允许根据程序需要动态分配N字节页。 通过首先通过高速缓存地址转换确定页面位置，然后直接索引到高速缓存中来访问高速缓存的内容。 缓存中的每个页面都存在起始页地址标签。 如果页面地址包含在当前页面查找中，则直接获取直列数据。 没有地址查找的直接提取加快了缓存访问周期。 如果地址不是当前页面，则会发生页面地址查找，以便在页面数据宏中获取正确的页面地址块索引。 如果发生小错误，则重新加载页面。
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公开(公告)号：US4709162A
公开(公告)日：1987-11-24
申请号：US908849
申请日：1986-09-18
IPC分类号： G11C11/413 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/003 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/01855 , H03K19/00315 , H03K19/018521
摘要： An off-chip driver circuit is provided which includes a pull-up device disposed between an output terminal and a first voltage dropping diode which is connected to a first voltage supply source and a first voltage limiting circuit connected to the common point between the pull-up device and the voltage dropping diode. The off-chip driver circuit further includes an input inverter circuit having an output connected to the control element of the pull-up device. The inverter circuit has a P-channel field effect transistor and an N-channel field effect transistor serially connected with a second voltage dropping diode which is connected to the first voltage supply source and a second voltage limiting circuit connected to the common point between the second voltage dropping diode and the P-channel field effect transistor of the input inverter. First and second switches are also provided to short out the first and second voltage dropping diodes, respectively, when all circuits connected to the output terminal use a common voltage supply. A pull-down device serially connected to a pass device is provided between the output terminal and a point of reference potential. A buffer circuit having an output connected to the pull-down device is coupled to a second voltage supply source having a voltage significantly lower than the voltage of the first voltage supply source.
摘要翻译： 提供了一种片外驱动电路，其包括设置在输出端和第一降压二极管之间的上拉装置，第一降压二极管连接到第一电压源和连接到第一电压限制电路之间的公共点的第一电压限制电路， 升压器件和降压二极管。 片外驱动电路还包括具有与上拉装置的控制元件连接的输出的输入反相器电路。 逆变器电路具有P沟道场效应晶体管和与第一电压源连接的第二降压二极管串联连接的N沟道场效应晶体管，以及与第二电压限制电路连接的第二电压限制电路 降压二极管和输入逆变器的P沟道场效应晶体管。 当连接到输出端子的所有电路都使用公共电压源时，也提供第一和第二开关来短路第一和第二降压二极管。 串联连接到通过装置的下拉装置设置在输出端子和参考点之间。 具有连接到下拉装置的输出的缓冲电路被耦合到具有显着低于第一电压源的电压的电压的第二电压源。
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10.发明授权Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability 有权用于调整字线上电压的方法和系统，以提高相对于SRAM单元稳定性的产量公开(公告)号：US08582351B2
公开(公告)日：2013-11-12
申请号：US12892191
申请日：2010-09-28
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译： 在制造的SRAM中设置字线上电压的方法。 在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。 然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。 提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。
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