发明授权
US5802330A Computer system including a plurality of real time peripheral devices having arbitration control feedback mechanisms 失效
计算机系统包括具有仲裁控制反馈机制的多个实时外围设备

  • 专利标题: Computer system including a plurality of real time peripheral devices having arbitration control feedback mechanisms
  • 专利标题(中): 计算机系统包括具有仲裁控制反馈机制的多个实时外围设备
  • 申请号: US644405
    申请日: 1996-05-01
  • 公开(公告)号: US5802330A
    公开(公告)日: 1998-09-01
  • 发明人: Drew J. Dutton
  • 申请人: Drew J. Dutton
  • 申请人地址: CA Sunnyvale
  • 专利权人: Advanced Micro Devices, Inc.
  • 当前专利权人: Advanced Micro Devices, Inc.
  • 当前专利权人地址: CA Sunnyvale
  • 主分类号: G06F13/364
  • IPC分类号: G06F13/364 G06F13/18
Computer system including a plurality of real time peripheral devices
having arbitration control feedback mechanisms
摘要:
A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of programmable registers are provided to receive configuration information for controlling the relative priority given to each of the bus masters when bus request contention occurs. One or more of the bus masters includes an arbitration feedback control circuit and feedback register for generating and storing a value to indicate whether the latency in obtaining the bus during a previous bus request phase was generous, was acceptable, or was longer than desired (i.e., the latency requirement for the device was either violated or the latency in obtaining the bus reached a near-critical point). If the value in the feedback register of a particular peripheral indicates the master desires faster access to the bus, an arbitration control unit of the bus arbiter increases a level of arbitration priority given to that master for future bus requests. Similarly, if the value in the feedback register of a peripheral indicates the master received ownership of the bus during a previous bus request phase with ample time, the arbitration control unit may decrease a level of arbitration priority given to the device.
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