An input signal processing circuit which prevents saturation of the input transistor. It has an input npn transistor QN1, a transistor QP1, the emitters of which are connected to the cathode terminal T.sub.CTD, and the collectors of which are connected to the collector of the input transistor. Transistors QP2,QP3 have emitters connected to the cathode terminal T.sub.CTD, and bases connected to the bases of transistor QP1. Transistor QN2 has its emitter connected to anode terminal T.sub.AND via resistor R5 and its collector connected to a common connecting point with the bases of transistors QP1,2. Transistor QN3 has its emitter connected to the anode terminal T.sub.AND, its base connected to the base of transistor QN2, and its collector connected to base and the collector of transistor QP2. A resistor R4 is connected between the collector of input transistor QN1 and the collector of third transistor QN2.