A flash memory array architecture comprising a flash memory array, first and second memory buffer, and I/O interface circuit which has several operating modes which permit data to be read from the flash memory array, several operating modes which permit data to be programmed into the flash memory array, and a mode for rewriting the data in the flash memory array.In the four read modes, one of the pages stored in the flash memory array is read, the data stored in either of first or second memory buffers is read, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers, the data in one of the pages of data stored in the flash memory array is read and then compared to the data read from either of first or second memory buffers. In the four write modes, data from an input stream is written into a selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array, data in either of first or second memory buffers is written into a previously erased page in the flash memory array, and data from an input stream is written into the selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array. In the auto page rewrite mode, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers. The data stored in the page of the flash memory array just read is erased, and then in the same cycle, the page of data stored in the selected first or second memory buffer is written into the erased page in the flash memory array.