A multi-processor computer system comprising a data storage device, a memory controller, and a plurality of processors. The data storage device has a plurality of memory lines, each memory line having a portion for alternatively storing data or, a set of GONE codes, a count value, and a processor identification code value. A memory controller coupled to the data storage alternatively stores and retrieves data or the GONE code, the count field value and the processor identification code value. At least one of the processors includes a cache memory and a cache memory controller. The cache memory controller compares a GONE code associated with the requested memory line with the contents of the requested memory line, and requests the contents of the requested memory line from a second of the processors in response to the comparison.