发明授权
US5829039A Memory control method/device for maintaining cache consistency with status bit indicating that a command is being processed with respect to a memory area 失效
用于保持高速缓存一致性的存储器控​​制方法/装置,用于指示相对于存储器区域正在处理命令的状态位

Memory control method/device for maintaining cache consistency with
status bit indicating that a command is being processed with respect to
a memory area
摘要:
A memory control method and a memory control device each suitable for information processing systems such as multiprocessing systems where plural data processing systems concurrently execute an operating process, and more particularly a memory control method and a memory control device each of which controls the data holding state of a buffer memory unit arranged in each of data processing units on a store-in basis to gain high speed access to the main storage unit. The memory control device issues a predetermined process command to be sent to the buffer memory unit in the data processing unit, and sets a flag showing a process under request, to a portion to be processed by the predetermined process command in a tag copying unit in the memory control device. Information regarding whether a block including a process request address exists in the buffer memory unit and whether the block is being processed currently are simultaneously obtained by retrieving only the tag copying unit. Thus, the address comparing unit can be omitted because no address comparison is needed. This structure reduces the amount of hardware and improves the port use efficiency, thus realizing the reduced system construction cost and improved processing speed.
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