公开(公告)号：US5829039A

公开(公告)日：1998-10-27

申请号：US869740

申请日：1997-06-05

申请人： Masatoshi Sugino ,  Naozumi Aoki ,  Yukihiko Kitano ,  Kenro Nagato

发明人： Masatoshi Sugino ,  Naozumi Aoki ,  Yukihiko Kitano ,  Kenro Nagato

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0822 ,  G06F12/0828 ,  G06F2212/621

摘要： A memory control method and a memory control device each suitable for information processing systems such as multiprocessing systems where plural data processing systems concurrently execute an operating process, and more particularly a memory control method and a memory control device each of which controls the data holding state of a buffer memory unit arranged in each of data processing units on a store-in basis to gain high speed access to the main storage unit. The memory control device issues a predetermined process command to be sent to the buffer memory unit in the data processing unit, and sets a flag showing a process under request, to a portion to be processed by the predetermined process command in a tag copying unit in the memory control device. Information regarding whether a block including a process request address exists in the buffer memory unit and whether the block is being processed currently are simultaneously obtained by retrieving only the tag copying unit. Thus, the address comparing unit can be omitted because no address comparison is needed. This structure reduces the amount of hardware and improves the port use efficiency, thus realizing the reduced system construction cost and improved processing speed.

摘要翻译： 一种存储器控制方法和存储器控制装置，其各自适用于诸如多处理系统的信息处理系统，其中多个处理系统同时执行操作处理，更具体地，存储器控制方法和存储器控制装置，每个控制装置控制数据保持状态 缓冲存储器单元，其被存储在每个数据处理单元中，以获得对主存储单元的高速访问。 存储器控制装置发出要发送到数据处理单元中的缓冲存储器单元的预定处理命令，并且通过标签复制单元中的预定处理命令将表示处理请求的标志设置为要处理的部分 存储器控制装置。 关于缓冲存储器单元中是否存在包括处理请求地址的块以及当前正在处理块的信息，通过仅检索标签复制单元来同时获得。 因此，可以省略地址比较单元，因为不需要地址比较。 这种结构减少了硬件的数量，提高了端口的使用效率，从而实现了系统建设成本的降低和处理速度的提高。

公开(公告)号：US20090240893A1

公开(公告)日：2009-09-24

申请号：US12330822

申请日：2008-12-09

申请人： Go Sugizaki ,  Aiichiro Inoue ,  Naozumi Aoki ,  Tsuyoshi Motokurumada

发明人： Go Sugizaki ,  Aiichiro Inoue ,  Naozumi Aoki ,  Tsuyoshi Motokurumada

IPC分类号： G06F12/08

CPC分类号： G06F12/0822

摘要： The present invention provides an information processing device, a memory control method, and a memory control device. In the information processing device that includes nodes each having a main memory and a processor including a cache memory, the system controller of at least one of the nodes is designed to include a holding unit that holds specific information about primary data present in the main memory of its subject node, with the cache data corresponding to the primary data not present in the cache memory of the nodes other than its subject node. With this structure, the latency of each memory access is shortened, and the throughput of each snoop operation is improved.

摘要翻译： 本发明提供一种信息处理装置，存储器控制方法和存储器控制装置。 在包括各自具有主存储器的节点和包括高速缓存存储器的处理器的信息处理设备中，至少一个节点的系统控制器被设计为包括保持单元，该保持单元保存有关主存储器中存在的主数据的特定信息 的主体节点，其中高速缓存数据对应于不存在于除了其主节点之外的节点的高速缓冲存储器中的主数据。 利用这种结构，每个存储器访问的延迟被缩短，并且提高了每次窥探操作的吞吐量。

公开(公告)号：US20080320360A1

公开(公告)日：2008-12-25

申请号：US12198577

申请日：2008-08-26

申请人： Hideyuki UNNO ,  Masaki Ukai ,  Naozumi Aoki

发明人： Hideyuki UNNO ,  Masaki Ukai ,  Naozumi Aoki

IPC分类号： G06F11/10

CPC分类号： H04L1/0042 ,  G06F11/349 ,  H04L1/0047 ,  H04L25/4915

摘要： A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).

摘要翻译： 发送侧设备（10）和接收侧设备（20）经由包括TAG位（31），数据位（32）和错误检测/校正ECC位（33）的总线（30）彼此连接。 发送侧装置（10）使用冗余比特反相电路（14）反相对应于触发信号（41和42）的ECC比特（33）的不同比特。 在接收侧设备（20）中，从错误检测/校正电路（22）接收到错误报告信号（26）的确定电路（24）从ECC位中的错误位的位置确定 （33），所述触发信号（41和42）中的哪一个已经从所述发送侧装置（10）发送。

公开(公告)号：US08301969B2

公开(公告)日：2012-10-30

申请号：US12198577

申请日：2008-08-26

申请人： Hideyuki Unno ,  Masaki Ukai ,  Naozumi Aoki

发明人： Hideyuki Unno ,  Masaki Ukai ,  Naozumi Aoki

IPC分类号： H03M13/00

CPC分类号： H04L1/0042 ,  G06F11/349 ,  H04L1/0047 ,  H04L25/4915

摘要： A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).

摘要翻译： 发送侧设备（10）和接收侧设备（20）经由包括TAG位（31），数据位（32）和错误检测/校正ECC位（33）的总线（30）彼此连接。 发送侧装置（10）使用冗余比特反相电路（14）反相对应于触发信号（41和42）的ECC比特（33）的不同比特。 在接收侧设备（20）中，从错误检测/校正电路（22）接收到错误报告信号（26）的确定电路（24）从ECC位中的错误位的位置确定 （33），所述触发信号（41和42）中的哪一个已经从所述发送侧装置（10）发送。

公开(公告)号：US08464004B2

公开(公告)日：2013-06-11

申请号：US12330822

申请日：2008-12-09

申请人： Go Sugizaki ,  Aiichiro Inoue ,  Naozumi Aoki ,  Tsuyoshi Motokurumada

发明人： Go Sugizaki ,  Aiichiro Inoue ,  Naozumi Aoki ,  Tsuyoshi Motokurumada

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0822

摘要： An information processing apparatus, a memory control method, and a memory control device are disclosed, the information processing apparatus including nodes each having a main memory, a processor including a cache memory, and a system controller. The system controller of at least one of the nodes includes a holding unit that holds address information corresponding to primary data stored in the main memory of its local node, and not cached in any of the cache memories of other nodes. The system controller of the at least one node may include local and global snoop control units, as well as a virtual tag expansion (VTAGx) unit, to maintain cache coherency, and under certain conditions, a snoop operation may be skipped or omitted.

摘要翻译： 公开了一种信息处理装置，存储器控制方法和存储器控制装置，该信息处理装置包括各自具有主存储器的节点，包括高速缓冲存储器的处理器和系统控制器。 至少一个节点的系统控制器包括保存单元，该保持单元保存对应于存储在其本地节点的主存储器中的主数据的地址信息，并且不保存在其他节点的任何高速缓冲存储器中。 至少一个节点的系统控制器可以包括本地和全局侦听控制单元以及虚拟标签扩展（VTAGx）单元，以维持高速缓存一致性，并且在某些情况下，可以跳过或省略窥探操作。

公开(公告)号：US4853929A

公开(公告)日：1989-08-01

申请号：US164483

申请日：1988-03-04

申请人： Isao Azuma ,  Miyuki Ishida ,  Naozumi Aoki

发明人： Isao Azuma ,  Miyuki Ishida ,  Naozumi Aoki

IPC分类号： G01R31/3185

CPC分类号： G01R31/318569 ,  G01R31/318558

摘要： An electronic circuit device able to diagnose a status-holding circuit by scanning, the device comprising a first plurality of integrated circuits each including a serial scan circuit for receiving serial data, generating an address value of a target status-holding circuit as parallel data from the received serial data, and selecting the target status-holding circuit having the generated address value, and a second plurality of integrated circuits each including a parallel scan circuit for receiving an address value of a target status-holding circuit as parallel data and selecting the target status-holding circuit having the received address value. Address information received as serial data being used for generating parallel address information, and address information received as parallel data being used for generating serial address information.

公开(公告)号：US20070050505A1

公开(公告)日：2007-03-01

申请号：US11333327

申请日：2006-01-18

申请人： Hideyuki Unno ,  Masaki Ukai ,  Naozumi Aoki

发明人： Hideyuki Unno ,  Masaki Ukai ,  Naozumi Aoki

IPC分类号： G06F15/173

CPC分类号： G06F13/404 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/35 ,  H04L49/503

摘要： An apparatus for controlling data transfer performed with a computer connected to a data bus, which performs data transfer in one direction, the apparatus includes a data transfer controlling unit that controls the data transfer with the computer by setting a data bandwidth of an input bus to be greater than a data bandwidth of an output bus, where the input bus transfers data to be input to the computer, and the output bus transfers data output by the computer.

摘要翻译： 一种用于控制数据传送的装置，该计算机连接到在一个方向上执行数据传输的数据总线，所述装置包括数据传送控制单元，其通过将输入总线的数据带宽设置为 大于输出总线的数据带宽，其中输入总线传送要输入到计算机的数据，并且输出总线传送计算机输出的数据。