A processor circuit configuration with a control processor and circuit blocks which are connected to the control processor through a bus. A testing device includes test decoders which are each assigned to a respective one of the circuit blocks. The test decoders receive control signals from the control processor and from a test logic, which is also connected to the bus, for controlling the circuit blocks. In a test mode, the test logic selects a given circuit block, deactivates all other circuit blocks, transmits test data through the bus to the given circuit block, activates the control processor, receives test data sent through the bus from the given circuit: block, evaluates the test data, and issues a corresponding result signal. The processing of the test data in the given circuit block is determined by the control processor.