发明授权
- 专利标题: 5v tolerant I/O circuit
- 专利标题(中): 5v容限I / O电路
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申请号: US797565申请日: 1997-02-07
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公开(公告)号: US5852375A公开(公告)日: 1998-12-22
- 发明人: Timothy Gerard Byrne , Brian T. Morley
- 申请人: Timothy Gerard Byrne , Brian T. Morley
- 申请人地址: IEX Dublin
- 专利权人: Silicon Systems Research Limited
- 当前专利权人: Silicon Systems Research Limited
- 当前专利权人地址: IEX Dublin
- 主分类号: H03K19/003
- IPC分类号: H03K19/003 ; H03K3/00 ; H02H3/20
摘要:
An integrated circuit has an I/O circuit that is connected to an I/O PAD. The I/O PAD may have greater voltage than the VDD associated with the integrated circuit so there is provided a switching circuit that is connected between the VDD and the I/O PAD. An output circuit is also provided that comprises n-channel transistors connected between the PAD and the ground. There is a cascode arrangement of p-channel transistors connected between the I/O PAD and VDD.
公开/授权文献
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