5v tolerant I/O circuit
    1.
    发明授权
    5v tolerant I/O circuit 失效
    5v容限I / O电路

    公开(公告)号:US5852375A

    公开(公告)日:1998-12-22

    申请号:US797565

    申请日:1997-02-07

    IPC分类号: H03K19/003 H03K3/00 H02H3/20

    CPC分类号: H03K19/00315

    摘要: An integrated circuit has an I/O circuit that is connected to an I/O PAD. The I/O PAD may have greater voltage than the VDD associated with the integrated circuit so there is provided a switching circuit that is connected between the VDD and the I/O PAD. An output circuit is also provided that comprises n-channel transistors connected between the PAD and the ground. There is a cascode arrangement of p-channel transistors connected between the I/O PAD and VDD.

    摘要翻译: 集成电路具有连接到I / O PAD的I / O电路。 I / O PAD可能具有比与集成电路相关的VDD更大的电压,因此提供了连接在VDD和I / O PAD之间的开关电路。 还提供了包括连接在PAD和地之间的n沟道晶体管的输出电路。 在I / O PAD和VDD之间连接有p沟道晶体管的共源共栅布置。