A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.