To provide FFT computing units, FFT computation devices, and pulse counters that can achieve computational precision using the smallest possible circuit size. FFT computing unit 602 comprises a data shift circuit for standardizing FFT computation target data to a specified bit width, adders/subtracters, multipliers, and data converters for standardizing the bit width to a certain bit width by truncating part of the output data of each computing unit, etc. FFT computation device comprises FFT computing unit 602, sensor 620, amplification circuit 621, gain control circuit 623, AD converter 622, first RAM 625 for sequentially storing the A/D conversion data, second RAM 626 for storing the FFT computation target data and the data being computed, coefficient ROM 101, and level determination circuit 624; and the level determination circuit determines the size of the data being transferred when the data is being transferred from RAM 1 to RAM 2, and the result is used for the data shift adjustment and gain control during FFT computation.