Invention Grant
- Patent Title: Memory capacity test method and computer system
- Patent Title (中): 内存容量测试方法和计算机系统
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Application No.: US801919Application Date: 1997-02-14
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Publication No.: US5854795APublication Date: 1998-12-29
- Inventor: Yuichi Osano
- Applicant: Yuichi Osano
- Applicant Address: JPX Yokohama
- Assignee: Kikusui Electronics Corporation
- Current Assignee: Kikusui Electronics Corporation
- Current Assignee Address: JPX Yokohama
- Priority: JPX8-029726 19960216
- Main IPC: G06F12/16
- IPC: G06F12/16 ; G06F11/22 ; G06F12/06 ; G11C29/08 ; G11C29/00
Abstract:
A memory capacity test method capable of confirming the memory capacity of an actually mounted memory in a short time in a memory system which mounts a memory only on a portion of a memory space. The method writes first data to a check address which is an n-th power of two, and then second data to the address 0, where the second data differs from the first data, and decides that the memory is not mounted on the check address if the data read from the check address disagrees with the first data. This is based on the fact that the check address actually points the address 0 when the memory is not mounted on the check address of the nth power of two, and hence the second data is written over the first data on the address 0 in that case.
Public/Granted literature
- US5310824A Water repellent aramids Public/Granted day:1994-05-10
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