发明授权
- 专利标题: Method of fabricating a high-density dynamic random-access memory
- 专利标题(中): 制造高密度动态随机存取存储器的方法
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申请号: US912686申请日: 1997-08-18
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公开(公告)号: US5856219A公开(公告)日: 1999-01-05
- 发明人: Yasushi Naito , Yutaka Ito , Yuichi Hirofuji
- 申请人: Yasushi Naito , Yutaka Ito , Yuichi Hirofuji
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JPX Osaka
- 优先权: JPX4-323361 19921202
- 主分类号: H01L23/522
- IPC分类号: H01L23/522 ; H01L21/768 ; H01L21/8239 ; H01L21/8242 ; H01L27/10 ; H01L27/108
摘要:
The invention relates to a high-density DRAM fabrication technique for forming a source/drain contact between word lines in a self-alignment manner, with the offset length between a source region and a drain region of a peripheral transistor maintained at an adequate value. After gate electrodes (i.e. word lines) are formed, a first insulating layer, which is thin enough not to block up space defined between the word lines, is deposited. The source/drain contact is etched as deep as the first insulating layer is thick to form an extraction electrode made of polycrystalline silicon. A second insulating layer is deposited until a spacer thickness (i.e. the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer) for determining the offset length is obtained. The first and second insulating layers are etched back for a distance corresponding to the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer so that a spacer (i.e. the residue of the insulating layers) is left on the side walls of the gate electrode. An implantation of highlevel impurities is performed to form heavily doped source and drain regions of a peripheral transistor. In-cell self-align contact is made possible while maintaining the offset length of the heavily doped source and drain regions