A full adder that operates rapidly with low power supply voltage and minimal power consumption, and further, that occupies a small area on a semiconductor element. A sum signal calculation circuit 10 of full adder 1 performs addition of input signals A and B and carry in signal C and outputs sum signal S.sub.out. Carry signal calculation circuit 16 outputs carry out signal C.sub.out corresponding to the combination of the logic values of input signals A and B and carry in signal C. Sum signal calculation circuit (10) is composed of addition signal generation circuit (12) and sum signal generation circuit (14). Addition signal generation circuit 12 performs XOR logic operations on input signals A and B. Sum signal generation circuit 14 outputs the results of full addition operations on inputs signals A and B and carry in signal C as sum signal S.sub.out, based on the results of XOR logic operations by addition signal generation circuit (12) and carry in signal C.