发明授权
US5875197A Addressable serial test system 失效
可寻址串口测试系统

Addressable serial test system
摘要:
An addressable serial test system employs a serial register with parallel outputs. Data is clocked into the serial register via a shift clock signal. A decoder is connected to a portion of the shift register's outputs and provides a selection signal dependent on the data clocked into the serial register. A system clock generates a system clock signal. A storage element includes a clock input coupled to the system clock signal, a data input, an output, a load input coupled to the selection signal, and a test data input coupled to another portion of the shift register's outputs. The storage element's output is alternately forced to a state indicative of the test data input by the selection signal and forced to a state indicative of the data input by the system clock. Structure is included to configure the serial register to read the contents of the storage element.
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