发明授权
US5880786A Apparatus for picture decoding having frame memories commonly connected
to one data bus and one address bus
失效
用于图像解码的装置,其具有共同连接到一个数据总线和一个地址总线的帧存储器
- 专利标题: Apparatus for picture decoding having frame memories commonly connected to one data bus and one address bus
- 专利标题(中): 用于图像解码的装置,其具有共同连接到一个数据总线和一个地址总线的帧存储器
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申请号: US490237申请日: 1995-06-14
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公开(公告)号: US5880786A公开(公告)日: 1999-03-09
- 发明人: Masuo Oku , Yukitoshi Tsuboi , Yukio Fujii , Hiroyuki Mizosoe
- 申请人: Masuo Oku , Yukitoshi Tsuboi , Yukio Fujii , Hiroyuki Mizosoe
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX6-133058 19940615; JPX6-150792 19940701; JPX6-155695 19940707
- 主分类号: G06T9/00
- IPC分类号: G06T9/00 ; H04N7/26 ; H04N7/50 ; H04N7/32
摘要:
An apparatus for picture decoding includes a decoder unit for obtaining decoded picture data by decoding coded data of a video signal coded by at least one of intra-frame coding (I frame), inter-frame coding (P frame), and frame-interpolation coding (B frame); a memory unit including a first frame memory, a second frame memory, and a third frame memory commonly connected to one data bus and one address bus; a display unit for reading the decoded picture data stored in the memory unit in field units based on a display synchronization signal and obtaining interlace-scanned display picture data; and a time control unit for reading the decoded picture data from the first frame memory and the second frame memory as reference frames for the B frame, and for controlling a time difference between a time of writing decoded picture data in the third frame memory, and a time of reading decoded picture data for display by the display unit, from the third frame memory, for reading decoded picture data before rewriting the same addresses, thereby attaining simultaneous read and write of the third frame memory at frame units.