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    Apparatus for picture decoding having frame memories commonly connected to one data bus and one address bus
    1.
    发明授权
    Apparatus for picture decoding having frame memories commonly connected to one data bus and one address bus 失效
    用于图像解码的装置，其具有共同连接到一个数据总线和一个地址总线的帧存储器

    公开(公告)号：US5880786A

    公开(公告)日：1999-03-09

    申请号：US490237

    申请日：1995-06-14

    申请人： Masuo Oku ,  Yukitoshi Tsuboi ,  Yukio Fujii ,  Hiroyuki Mizosoe

    发明人： Masuo Oku ,  Yukitoshi Tsuboi ,  Yukio Fujii ,  Hiroyuki Mizosoe

    IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  H04N7/32

    CPC分类号： H04N19/433 ,  H04N19/42 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61

    摘要： An apparatus for picture decoding includes a decoder unit for obtaining decoded picture data by decoding coded data of a video signal coded by at least one of intra-frame coding (I frame), inter-frame coding (P frame), and frame-interpolation coding (B frame); a memory unit including a first frame memory, a second frame memory, and a third frame memory commonly connected to one data bus and one address bus; a display unit for reading the decoded picture data stored in the memory unit in field units based on a display synchronization signal and obtaining interlace-scanned display picture data; and a time control unit for reading the decoded picture data from the first frame memory and the second frame memory as reference frames for the B frame, and for controlling a time difference between a time of writing decoded picture data in the third frame memory, and a time of reading decoded picture data for display by the display unit, from the third frame memory, for reading decoded picture data before rewriting the same addresses, thereby attaining simultaneous read and write of the third frame memory at frame units.

    摘要翻译： 一种用于图像解码的装置包括：解码器单元，用于通过对通过帧内编码（I帧），帧间编码（P帧）和帧插值中的至少一个编码的视频信号的编码数据进行解码来获得解码图像数据 编码（B帧）; 存储单元，包括共同连接到一个数据总线和一个地址总线的第一帧存储器，第二帧存储器和第三帧存储器; 显示单元，用于基于显示同步信号以场为单位读取存储在存储器单元中的解码图像数据，并获得隔行扫描显示图像数据; 以及时间控制单元，用于从第一帧存储器和第二帧存储器读取解码图像数据作为B帧的参考帧，并且用于控制在第三帧存储器中写入解码图像数据的时间之间的时间差;以及 从第三帧存储器读取由显示单元显示的解码图像数据的时间，用于在重写相同的地址之前读取解码的图像数据，从而以帧为单位同时读取和写入第三帧存储器。

    Decoding device for decoding a variety of code signals
    2.
    发明授权
    Decoding device for decoding a variety of code signals 失效
    解码设备，用于解码各种代码信号

    公开(公告)号：US5675331A

    公开(公告)日：1997-10-07

    申请号：US572100

    申请日：1995-12-14

    申请人： Hiromi Watanabe ,  Hiroki Mizosoe ,  Yukitoshi Tsuboi ,  Takayuki Miyo ,  Shuji Shinohara ,  Masuo Oku

    发明人： Hiromi Watanabe ,  Hiroki Mizosoe ,  Yukitoshi Tsuboi ,  Takayuki Miyo ,  Shuji Shinohara ,  Masuo Oku

    IPC分类号： H03M7/30 ,  H03M7/40 ,  H03M7/42

    CPC分类号： H03M7/425 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91

    摘要： A decoding device is provided including a code FIFO memory unit for sequentially storing a bit stream, a barrel shifter for shifting and then outputting codes properly, an accumulator for computing the shift amount of the barrel shifter and issuing a request to read data to the code FIFO memory unit, a DCT coefficient decoder for decoding DCT coefficients, a variable-length code decoder for decoding variable-length codes other than DCT coefficients, a fixed-length code decoder for decoding fixed-length codes, a register unit for storing decoded data, a decoding controller for controlling the decoders in accordance with the decoded data stored in the register unit and decoded data output by the decoders and a memory controller for controlling operations to store DCT coefficients in a memory unit A. The DCT coefficient decoder, the variable-length code decoder and the fixed-length code decoder are connected in parallel to the output of the barrel shifter and the memory controller is controlled by the decoding controller. By virtue of this structure, the decoding device is capable decoding a bit stream comprising variable-length codes mixed with fixed-length codes. The decoding device is also capable of changing processing of a next code in accordance with decoded codes. Further, these operations can be implemented by means of a simple and reasonable configuration. On top of that, the process of decoding codes at a required high speed is carried out by an independent circuit, allowing the processing power of the decoding circuit to be enhanced.

    摘要翻译： 提供一种解码装置，包括用于顺序存储位流的代码FIFO存储器单元，用于移位并随后正确输出代码的桶形移位器，用于计算桶形移位器的移位量并发出向代码读取数据的请求的累加器 FIFO存储单元，用于解码DCT系数的DCT系数解码器，用于解码除DCT系数之外的可变长度码的可变长度码解码器，用于解码固定长度码的固定长度码解码器，用于存储解码数据的寄存器单元 ，解码控制器，用于根据存储在寄存器单元中的解码数据和由解码器输出的解码数据来控制解码器;以及存储器控制器，用于控制将DCT系数存储在存储单元A中的操作。DCT系数解码器，变量 长码解码器和固定长度码解码器并联连接到桶形移位器的输出，并且存储器控制器是连续的 由解码控制器滚动。 通过这种结构，解码装置能够解码包含与固定长度码混合的可变长度码的比特流。 解码装置还能够根据解码的代码改变下一个代码的处理。 此外，这些操作可以通过简单合理的配置来实现。 此外，通过独立电路进行以所需高速解码的处理，能够提高解码电路的处理能力。

    Digital video signal recording and reproducing apparatus and method for setting a number of compression blocks according to different operational modes
    3.
    发明授权
    Digital video signal recording and reproducing apparatus and method for setting a number of compression blocks according to different operational modes 失效
    数字视频信号记录和再现装置和方法，用于根据不同的操作模式设置多个压缩块

    公开(公告)号：US5550640A

    公开(公告)日：1996-08-27

    申请号：US273626

    申请日：1994-07-12

    申请人： Yukitoshi Tsuboi ,  Masuo Oku ,  Masaru Takahashi ,  Kenji Ichige

    发明人： Yukitoshi Tsuboi ,  Masuo Oku ,  Masaru Takahashi ,  Kenji Ichige

    IPC分类号： G11B20/10 ,  G11B20/12 ,  H04N5/92 ,  H04N5/926 ,  H04N5/937 ,  H04N5/945 ,  H04N9/79 ,  H04N9/804 ,  H04N9/877 ,  H04N9/888 ,  H04N5/76

    CPC分类号： H04N9/877 ,  H04N5/9264 ,  H04N5/937 ,  H04N5/945 ,  H04N9/7925 ,  H04N9/8042 ,  H04N9/8047 ,  H04N9/888

    摘要： A digital video signal recording and reproducing apparatus and method wherein a basic block is constituted by a plurality of pixels of video signals. A picture data compressing unit effects data compression of the video signals so that a compression data quantity after data compression becomes a constant with respect to a compression block constituted by a plurality of the basic blocks, and the compressed data o the video signals are recorded on a data recording medium. A compression block setting sets a number of the basic blocks to constitute the compression block in response to different operation modes of the digital video signal recording and reproducing apparatus which are different in at least one of resolution of the video signals, recording time and data compression system, and controls the picture data compressing unit so that the number of the compression blocks of the video signals recorded on one track of the data recording medium after data compression by the picture data compressing unit becomes M in a first operation mode, where M is a positive integer, and the number of the compression blocks becomes a positive integer in each of the other operation modes.

    摘要翻译： 一种数字视频信号记录和再现装置和方法，其中基本块由视频信号的多个像素构成。 图像数据压缩单元对视频信号进行数据压缩，使得数据压缩后的压缩数据量相对于由多个基本块构成的压缩块变为常数，视频信号的压缩数据被记录在 数据记录介质。 压缩块设置响应于视频信号的分辨率，记录时间和数据压缩中的至少一个而不同的数字视频信号记录和再现设备的不同操作模式，设置构成压缩块的基本块的数量 系统，并且控制图像数据压缩单元，使得在图像数据压缩单元的数据压缩之后记录在数据记录介质的一个轨道上的视频信号的压缩块的数量在第一操作模式中变为M，其中M是 正整数，并且压缩块的数量在每个其他操作模式中变为正整数。

    Picture signal digital processing unit
    7.
    发明授权
    Picture signal digital processing unit 失效
    图像信号数字处理单元

    公开(公告)号：US5636316A

    公开(公告)日：1997-06-03

    申请号：US283685

    申请日：1994-08-01

    申请人： Masuo Oku ,  Yukio Fujii ,  Masaru Takahashi ,  Kenji Ichige ,  Keizo Nishimura ,  Atsuo Suga ,  Shigemitsu Higuchi ,  Tomohide Sorihashi

    发明人： Masuo Oku ,  Yukio Fujii ,  Masaru Takahashi ,  Kenji Ichige ,  Keizo Nishimura ,  Atsuo Suga ,  Shigemitsu Higuchi ,  Tomohide Sorihashi

    IPC分类号： H04N9/797 ,  H04N9/804 ,  H04N5/92

    CPC分类号： H04N9/8047 ,  H04N9/7973

    摘要： A digital processing unit for converting a digital picture signal into data by blocks and for correction encoding a variable-length encoded signal. This digital processing unit includes a digital data compressing section for dividing a picture signal into a plurality of number of blocks, and compressingly outputting digital data of this picture signal based on a processing unit of one or a few blocks, a buffer section for sequentially storing the digital data, and an error correction encoding section for sequentially reading the digital data from this buffer section, and structuring an inner code for each inner block structured by this digital data and structuring an outer code for each predetermined unit of inner blocks, to thereby structure two-dimensional error correction code blocks, to output an error correction code signal. Further, the error correction encoding section has the length of the digital data of the picture signal included in the inner code set to be equal to or larger than a mean code length of predetermined compressed blocks.

    摘要翻译： 一种数字处理单元，用于将数字图像信号转换成数据块并用于对可变长度编码信号进行校正编码。 该数字处理单元包括数字数据压缩部分，用于将图像信号分成多个块，并且基于一个或几个块的处理单元压缩输出该图像信号的数字数据;缓冲部分，用于顺序存储 数字数据和纠错编码部分，用于从该缓冲器部分顺序读取数字数据，并且构造由该数字数据构成的每个内部块的内部代码，并为每个内部块的每个预定单位构成外部代码，由此 结构二维纠错码块，输出纠错码信号。 此外，纠错编码部分将内部码中包括的图像信号的数字数据的长度设置为等于或大于预定压缩块的平均码长。