A method of forming a self-aligned contact of a DRAM cell includes providing a substrate having a MOS transistor. The MOS transistor includes a gate and a source/drain region. A first insulating layer, a second insulating layer and a third insulating layer are formed over the surface of the substrate in succession. The third insulating layer is planarized. A contact window mask is formed above the third insulating layer. Using the contact window mask as a cover, the third insulating layer is removed using anisotropic dry etching and isotropic wet etching. Then, a portion of the second insulating layer and a portion of the first insulating layer are removed sequentially to expose the source/drain region so that a self-aligned contact is formed.