发明授权
US5892699A Method and apparatus for optimizing dependent operand flow within a
multiplier using recoding logic
失效
用于使用重新编码逻辑优化乘数内的相关操作数流的方法和装置
- 专利标题: Method and apparatus for optimizing dependent operand flow within a multiplier using recoding logic
- 专利标题(中): 用于使用重新编码逻辑优化乘数内的相关操作数流的方法和装置
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申请号: US931859申请日: 1997-09-16
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公开(公告)号: US5892699A公开(公告)日: 1999-04-06
- 发明人: John L. Duncan , Albert J. Loper, Jr.
- 申请人: John L. Duncan , Albert J. Loper, Jr.
- 申请人地址: CA Santa Clara
- 专利权人: Integrated Device Technology, Inc.
- 当前专利权人: Integrated Device Technology, Inc.
- 当前专利权人地址: CA Santa Clara
- 主分类号: G06F7/52
- IPC分类号: G06F7/52
摘要:
A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.
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