公开(公告)号：US08533434B2

公开(公告)日：2013-09-10

申请号：US12572045

申请日：2009-10-01

申请人： John L. Duncan ,  Thomas C. McDonald

发明人： John L. Duncan ,  Thomas C. McDonald

IPC分类号： G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/30152 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F12/0862 ,  G06F2212/6028

摘要： An apparatus efficiently determines the length of an instruction within a stream of instruction bytes processed by a microprocessor having a variable instruction length instruction set architecture. The apparatus includes combinatorial logic associated with each instruction byte of the stream, each configured to receive the associated instruction byte and the next instruction byte of the stream and to generate in response thereto a first length, a second length, and a select control. A multiplexor associated with each of the combinatorial logic selects and outputs one of the following inputs based on the select control received from the combinatorial logic: a zero input and the second length received from the combinatorial logic associated with each of the next three instruction bytes of the stream. An adder associated with each of the combinatorial logic and multiplexor adds the first length and the output of the multiplexor to generate the length of the instruction.

摘要翻译： 一种装置有效地确定由具有可变指令长度指令集架构的微处理器处理的指令字节流内的指令的长度。 该装置包括与流的每个指令字节相关联的组合逻辑，每个指令字节被配置为接收流的相关联的指令字节和下一指令字节，并响应于此生成第一长度，第二长度和选择控制。 与组合逻辑中的每一个相关联的多路复用器基于从组合逻辑接收的选择控制来选择并输出以下输入之一：从与下一个三个指令字节中的每一个相关联的组合逻辑接收到的零输入和第二长度 流。 与组合逻辑和多路复用器中的每一个相关联的加法器将多路复用器的第一长度和输出相加以生成指令的长度。

公开(公告)号：US08443172B2

公开(公告)日：2013-05-14

申请号：US12571997

申请日：2009-10-01

申请人： Thomas C. McDonald ,  John L. Duncan

发明人： Thomas C. McDonald ,  John L. Duncan

IPC分类号： G06F9/30

摘要： An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes. If during the first clock cycle and any of N subsequent clock cycles the decode logic indicates that one of the predetermined number of instruction bytes specifies a length-modifying prefix, the operand/address size logic provides to the decode logic on the next clock cycle the address/operand size specified by the length-modifying prefix to use to generate the start and end marks.

公开(公告)号：US08013649B2

公开(公告)日：2011-09-06

申请号：US12574798

申请日：2009-10-07

申请人： John L. Duncan

发明人： John L. Duncan

IPC分类号： H03K3/356

CPC分类号： H03K3/356121 ,  H03K3/012

摘要： A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.

摘要翻译： 动态时钟反馈锁存器包括反馈路径，其响应于时钟输入变低而产生作为数据输入的函数的输出上的数据值，并且在从时钟输入变为高的延迟之后在输出上产生锁存值。 当时钟输入为低电平时，第一晶体管对节点进行高电压预充电。 第二晶体管提供用于在节点输入为高时将节点从预充电值引导到低电平的漏极路径。 如果数据值较高，则输出在延迟期间控制第三晶体管，以将数据值降低，并将其保持在较高值。 反馈路径在延迟之后在输出上产生预定的锁存值，使得数据值的反相值被锁存到节点上。

公开(公告)号：US5892699A

公开(公告)日：1999-04-06

申请号：US931859

申请日：1997-09-16

申请人： John L. Duncan ,  Albert J. Loper, Jr.

发明人： John L. Duncan ,  Albert J. Loper, Jr.

IPC分类号： G06F7/52

CPC分类号： G06F7/5338

摘要： A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.

摘要翻译： 提供了一种用于消除Booth重新编码逻辑所需的建立时间的方法和装置。 联锁电路检测何时第二乘法指令指定将先前乘法指令的乘积作为布斯编码逻辑的乘数输入。 互锁逻辑控制多路复用输入到乘法器路径和被乘数路径。 当互锁逻辑检测到这样的乘法器依赖性时，将先前的乘法指令的乘积提供给乘法器路径，并且乘法器被提供给乘法器路径。 因此，在先前乘法指令的乘积可用之前，可以将第二乘法指令的乘法器提供给布斯编码逻辑。 因此，在执行第二乘法指令之前，设置布局重新编码逻辑。

公开(公告)号：US5291334A

公开(公告)日：1994-03-01

申请号：US827794

申请日：1992-01-30

申请人： Allan Wirth ,  Andrew J. Jankevics ,  Franklin M. Landers ,  Theresa L. Bruno ,  Dante P. D'Amato ,  Lawrence E. Schmutz ,  Lawrence H. Gilligan ,  John L. Duncan

发明人： Allan Wirth ,  Andrew J. Jankevics ,  Franklin M. Landers ,  Theresa L. Bruno ,  Dante P. D'Amato ,  Lawrence E. Schmutz ,  Lawrence H. Gilligan ,  John L. Duncan

IPC分类号： G02B3/00 ,  G06T3/40 ,  G02B27/10 ,  G02B13/06

CPC分类号： G06T3/005 ,  G02B3/0056 ,  G02B3/0062 ,  G02B3/02

摘要： A panoramic imaging system is formed from select configurations of micro-optic multiplets (MOM) comprised of two microlens modules (MLM). The MLMs themselves are formed from arrays of microlenses. The present panoramic imaging system is characterized by the two MLMs configured on concentric approximately spherical surfaces. The optic axis of each of the microlenses is tilted slightly with respect to its neighbor to allow for proper alignment of images to form a single primary image on a substantially spherical global image surface.

摘要翻译： 全景成像系统由由两个微透镜模块（MLM）组成的微光学多重（MOM）的选择配置形成。 MLM本身由微透镜阵列形成。 本全景成像系统的特征在于两个MLM配置在同心的大致球形表面上。 每个微透镜的光轴相对于其相邻部分稍微倾斜，以允许图像的适当对准以在基本上球面的全局图像表面上形成单个主图像。

公开(公告)号：US3968712A

公开(公告)日：1976-07-13

申请号：US573657

申请日：1975-05-01

申请人： John L. Duncan

发明人： John L. Duncan

IPC分类号： B23D47/02 ,  B23Q1/03 ,  B23D19/00 ,  B26D1/18 ,  B27B5/28 ,  B27B27/04

CPC分类号： B23Q1/032 ,  B23D47/025 ,  Y10T29/49861 ,  Y10T83/773

摘要： A method and article of fabricating a table comprising the steps of making a lightweight metal frame having a plurality of channels, the edges of which are slightly overlapped by steel plates placed on and connected to the frame. The top surface of the steel plates is machined to render the same coplanar.The frame has orthogonal ribs, and a plurality of bosses formed with apertures therethrough for passage of connecting screws which thread into tapped holes formed in the steel plates. Any excessive length of the screws will be cut off during the machining operation.

摘要翻译： 一种制造桌子的方法和制品，包括以下步骤：制造具有多个通道的轻质金属框架，其边缘与放置在框架上并连接到框架上的钢板稍微重叠。 钢板的顶面加工成相同的共面。

公开(公告)号：US08612727B2

公开(公告)日：2013-12-17

申请号：US12571997

申请日：2009-10-01

申请人： Thomas C. McDonald ,  John L. Duncan

发明人： Thomas C. McDonald ,  John L. Duncan

IPC分类号： G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/30152 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F12/0862 ,  G06F2212/6028

摘要： An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes. If during the first clock cycle and any of N subsequent clock cycles the decode logic indicates that one of the predetermined number of instruction bytes specifies a length-modifying prefix, the operand/address size logic provides to the decode logic on the next clock cycle the address/operand size specified by the length-modifying prefix to use to generate the start and end marks.

摘要翻译： 一种微处理器中的装置，其具有指令集结构，其中指令可以包括用于选择除默认地址/操作数大小之外的地址/操作数大小的长度修改前缀，其中该装置标记起始字节和结束字节 指令字节中的每条指令。 解码逻辑解码预定数量的指令字节的每个指令字节，以确定指令字节是否指定长度修改前缀，并且基于地址/操作数大小为每个指令字节生成起始标记和结束标记。 操作数/地址大小逻辑为解码逻辑提供了默认的操作数/地址大小，用于在第一时钟周期期间产生起始和终止标志，在此时间周期内解码逻辑解码预定数量的指令字节。 如果在第一时钟周期和N个随后的时钟周期中的任何一个周期中，解码逻辑指示预定数量的指令字节中的一个指定长度修改前缀，则操作数/地址大小逻辑在下一个时钟周期提供给解码逻辑 由用于生成开始和结束标记的长度修改前缀指定的地址/操作数大小。

公开(公告)号：US20100299500A1

公开(公告)日：2010-11-25

申请号：US12572002

申请日：2009-10-01

申请人： Thomas C. McDonald ,  John L. Duncan

发明人： Thomas C. McDonald ,  John L. Duncan

IPC分类号： G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/30152 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F12/0862 ,  G06F2212/6028

摘要： In a microprocessor that has an instruction set architecture in which the instructions may include a variable number of prefix bytes, an apparatus for efficiently extracting instructions from a stream of undifferentiated instruction bytes. Decode logic determines which byte is an opcode byte for each instruction of a plurality of instructions within the stream of undifferentiated instruction bytes. The opcode byte is the first non-prefix byte of the instruction. The decode logic accumulates prefix information onto the opcode byte of the instruction for each instruction of the plurality of instructions. A queue holds the stream of undifferentiated instruction bytes and the accumulated prefix information. Extraction logic extracts the plurality of instructions from the queue in one clock cycle independent of the number of prefix bytes included in each of the plurality of instructions.

摘要翻译： 在具有指令集架构的微处理器中，指令可以包括可变数量的前缀字节，用于从未分化指令字节流高效地提取指令的装置。 解码逻辑确定哪个字节是未分化指令字节流内的多条指令的每个指令的操作码字节。 操作码字节是指令的第一个非前缀字节。 解码逻辑将前缀信息累积到多个指令中的每个指令的指令的操作码字节上。 队列保存未分化指令字节流和累加的前缀信息。 提取逻辑在一个时钟周期内从队列中提取多个指令，而与包含在多个指令中的每个指令中的前缀字节的数量无关。

公开(公告)号：US20100299497A1

公开(公告)日：2010-11-25

申请号：US12572045

申请日：2009-10-01

申请人： John L. Duncan ,  Thomas C. McDonald

发明人： John L. Duncan ,  Thomas C. McDonald

IPC分类号： G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/30152 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F12/0862 ,  G06F2212/6028

摘要： An apparatus efficiently determines the length of an instruction within a stream of instruction bytes processed by a microprocessor having a variable instruction length instruction set architecture. The apparatus includes combinatorial logic associated with each instruction byte of the stream, each configured to receive the associated instruction byte and the next instruction byte of the stream and to generate in response thereto a first length, a second length, and a select control. A multiplexor associated with each of the combinatorial logic selects and outputs one of the following inputs based on the select control received from the combinatorial logic: a zero input and the second length received from the combinatorial logic associated with each of the next three instruction bytes of the stream. An adder associated with each of the combinatorial logic and multiplexor adds the first length and the output of the multiplexor to generate the length of the instruction.

摘要翻译： 一种装置有效地确定由具有可变指令长度指令集架构的微处理器处理的指令字节流内的指令的长度。 该装置包括与流的每个指令字节相关联的组合逻辑，每个指令字节被配置为接收流的相关联的指令字节和下一指令字节，并响应于此生成第一长度，第二长度和选择控制。 与组合逻辑中的每一个相关联的多路复用器基于从组合逻辑接收的选择控制来选择并输出以下输入之一：从与下一个三个指令字节中的每一个相关联的组合逻辑接收到的零输入和第二长度 流。 与组合逻辑和多路复用器中的每一个相关联的加法器将多路复用器的第一长度和输出相加以生成指令的长度。

公开(公告)号：US5550774A

公开(公告)日：1996-08-27

申请号：US523663

申请日：1995-09-05

申请人： Michael L. Brauer ,  Paul A. Reed ,  John L. Duncan

发明人： Michael L. Brauer ,  Paul A. Reed ,  John L. Duncan

IPC分类号： G06F12/08 ,  G11C8/00

CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

摘要： A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers (48, 50, 52, 54). The memory cache executes a parallel tag and data array access but does not enable any sense amplifier until a comparator indicates a cache hit. Consequently, the memory cache is suitable for use where power consumption and speed are equally important design constraints.

摘要翻译： 存储器高速缓存（46）具有多个标签阵列（20,22,24,26），多个比较器（38,40,42,44），多个数据阵列（12,14,16,18） ，以及多个读出放大器（48,50,52,54）。 存储器缓存执行并行标签和数据数组访问，但在比较器指示高速缓存命中之前不启用任何读出放大器。 因此，存储器高速缓存适用于功耗和速度同样重要的设计约束。