发明授权
US5892724A NAND-type dynamic RAM having temporary storage register and sense
amplifier coupled to multi-open bit lines
失效
NAND型动态RAM具有耦合到多开位线的临时存储寄存器和读出放大器
- 专利标题： NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines
- 专利标题（中）： NAND型动态RAM具有耦合到多开位线的临时存储寄存器和读出放大器
-
申请号： US848152申请日： 1997-04-29
-
公开(公告)号： US5892724A公开(公告)日： 1999-04-06
- 发明人: Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
- 申请人： Takehiro Hasegawa , Yukihito Oowaki , Fujio Masuoka , Ryu Ogiwara , Shinichiro Shiratake , Shigeyoshi Watanabe
- 申请人地址： JPX Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX3-329474 19911118; JPX4-65122 19920323; JPX4-299867 19921110; JPX4-331238 19921118
- 主分类号： G11C7/10
- IPC分类号： G11C7/10 ; G11C11/404 ; G11C11/4096 ; G11C11/4097 ; G11C8/00
摘要：
A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.
公开/授权文献
- US5329494A Memory cell array divided type semiconductor memory device 公开/授权日：1994-07-12
信息查询
