The microtip housing cavity in a cold cathode display was formed by selecting for the dielectric layer surrounding it a material whose etch rate (for the same etchant) was 3 to 20 times faster than the etch rate of the gate layer. Specifically, a gaseous etchant that included CHF.sub.3, CH.sub.4, CO, or CO and C.sub.4 F.sub.8 was used to form the cavity in a layer consisting of silicon oxide containing between about 3 and 10 weight % boron and between about 3 and 10 weight % phosphorus, deposited by chemical vapor deposition at pressures somewhat less than atmospheric (commonly referred to as SABPSG or sub-atmospheric boro-phosphosilicate glass). The gate layer consisted of phosphorus-doped polysilicon. Using this combination, once the gate opening had been etched, etching of the cavity proceeded very rapidly with little increase in the width of the gate opening. Thus the cavity was formed in a single mask, single etchant process.