公开(公告)号：US5792672A

公开(公告)日：1998-08-11

申请号：US618891

申请日：1996-03-20

申请人： Lap Chan ,  Simon Chooi Yen Meng ,  Tony Chan

发明人： Lap Chan ,  Simon Chooi Yen Meng ,  Tony Chan

IPC分类号： G03F7/42 ,  H01L21/311 ,  H01L21/465

CPC分类号： H01L21/31138 ,  G03F7/427

摘要： An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been created. The method is a two step process, in which a first stripping step is in a plasma containing O.sub.2 and H.sub.2 O and a second stripping step is in a plasma containing O.sub.2.

摘要翻译： 已经产生了一种用于在含氯等离子体中蚀刻图案之后从蚀刻铝图案去除光致抗蚀剂掩模的改进方法。 该方法是两步法，其中第一汽提步骤在含有O 2和H 2 O的等离子体中，第二汽提步骤在含有O 2的等离子体中。

公开(公告)号：US5693178A

公开(公告)日：1997-12-02

申请号：US559050

申请日：1996-01-18

申请人： Lap Chan ,  Simon Chooi

发明人： Lap Chan ,  Simon Chooi

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L22/34

摘要： A microloading quantification apparatus is comprising a supporting substrate, a first bonding pad deposited upon the supporting substrate, a second bonding pad deposited upon the supporting substrate, and an etched conductive pattern deposited upon the supporting substrate and operably connected to the first bonding pad and the second bonding pad. Methods for the formation and application of the microloading quantification apparatus to quantify the variation of the microloading effect as a result of modifications of the set of parameters of integrated circuit processing particularly those of the plasma dry etch are described.

摘要翻译： 微量负载量化装置包括支撑衬底，沉积在支撑衬底上的第一焊盘，沉积在支撑衬底上的第二焊盘，以及沉积在支撑衬底上并可操作地连接到第一焊盘和 第二粘接垫。 描述了形成和应用微量负荷量化装置的方法，以量化由于集成电路处理的一组参数，特别是等离子体干蚀刻的参数组的修改而导致的微加载效应的变化。

公开(公告)号：US5893787A

公开(公告)日：1999-04-13

申请号：US805877

申请日：1997-03-03

申请人： Lap Chan ,  Simon Chooi

发明人： Lap Chan ,  Simon Chooi

IPC分类号： H01J9/02

CPC分类号： H01J9/025

摘要： The microtip housing cavity in a cold cathode display was formed by selecting for the dielectric layer surrounding it a material whose etch rate (for the same etchant) was 3 to 20 times faster than the etch rate of the gate layer. Specifically, a gaseous etchant that included CHF.sub.3, CH.sub.4, CO, or CO and C.sub.4 F.sub.8 was used to form the cavity in a layer consisting of silicon oxide containing between about 3 and 10 weight % boron and between about 3 and 10 weight % phosphorus, deposited by chemical vapor deposition at pressures somewhat less than atmospheric (commonly referred to as SABPSG or sub-atmospheric boro-phosphosilicate glass). The gate layer consisted of phosphorus-doped polysilicon. Using this combination, once the gate opening had been etched, etching of the cavity proceeded very rapidly with little increase in the width of the gate opening. Thus the cavity was formed in a single mask, single etchant process.

摘要翻译： 冷阴极显示器中的微尖端壳体腔通过选择围绕其的介电层形成，其蚀刻速率（相同蚀刻剂）的蚀刻速率比栅极层的蚀刻速率快3至20倍。 具体地，使用包括CHF 3，CH 4，CO或CO和C 4 F 8的气体蚀刻剂在由含有约3至10重量％硼和约3至10重量％磷之间的氧化硅组成的层中形成空腔， 通过化学气相沉积在小于大气压（通常称为SABPSG或次大气硼硅磷酸盐玻璃）的压力下沉积。 栅极层由磷掺杂多晶硅组成。 使用这种组合，一旦栅极开口被蚀刻，腔的蚀刻就非常迅速地进行，门开口的宽度几乎没有增加。 因此，腔形成在单个掩模中，单一蚀刻过程。

公开(公告)号：US09262732B2

公开(公告)日：2016-02-16

申请号：US13166501

申请日：2011-06-22

申请人： Bin Duan ,  Lap Chan

发明人： Bin Duan ,  Lap Chan

IPC分类号： G06Q10/06 ,  H04W64/00

CPC分类号： G06Q10/0631 ,  H04W64/006

摘要： A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.

摘要翻译： 跟踪企业数据处理环境中的动作项目的系统和方法。 该方法包括由客户端从服务器接收包括位置的动作项目。 该方法还包括由客户端在与该动作项目相关的位置处执行登记。 该方法还包括由客户端执行与该动作项目相关的退房。 该方法还包括由客户端改变动作项目的状态。 以这种方式，可以开发一个行动项目和状态的数据库，用于更有效的业务协作和业务管理。

公开(公告)号：US20140123068A1

公开(公告)日：2014-05-01

申请号：US13661687

申请日：2012-10-26

申请人： Lap Chan

发明人： Lap Chan

IPC分类号： G06F3/048

CPC分类号： G06F3/04817 ,  G06F3/0482 ,  G06F3/0486 ,  G06F3/04886 ,  H04M1/72519

摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, if second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.

摘要翻译： 描述了管理内容的示例系统和方法。 在一个实现中，一种方法访问第一组数据，如果是第二组数据，则菜单数据。 菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。 该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。 该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

公开(公告)号：US07932152B2

公开(公告)日：2011-04-26

申请号：US12025789

申请日：2008-02-05

申请人： Will Wong ,  Lap Chan ,  Alan Lek

发明人： Will Wong ,  Lap Chan ,  Alan Lek

IPC分类号： H01L21/8234

CPC分类号： H01L21/28202 ,  H01L21/28035 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.

摘要翻译： 一种在基板上形成集成电路结构的方法，所述基板包括主区域和次区域。 在衬底上形成第一厚度的第一材料的第一层。 第一层的一部分在主区域上被去除以暴露衬底。 该结构暴露于氧化介质。 这形成例如基板的氧化物材料主区域的第二层。 第二层具有第二厚度。 另外，所述第一层的至少一部分被转换成例如氮氧化物材料的第三层。 第三层具有第三厚度。

公开(公告)号：US20050196931A1

公开(公告)日：2005-09-08

申请号：US11123748

申请日：2005-05-04

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-fu Chu

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US20050156269A1

公开(公告)日：2005-07-21

申请号：US11081908

申请日：2005-03-15

申请人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

发明人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L27/095

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US20050145953A1

公开(公告)日：2005-07-07

申请号：US10752454

申请日：2004-01-05

申请人： Lap Chan ,  Jia Zheng ,  Purakh Verma ,  Jian Li ,  Shao-fu Chu

发明人： Lap Chan ,  Jia Zheng ,  Purakh Verma ,  Jian Li ,  Shao-fu Chu

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L31/113

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L27/0623

摘要： A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.

摘要翻译： 一种制造包括具有栅极结构的CMOS晶体管的BiCMOS集成电路的方法和具有外在基极结构的异质结双极晶体管。 提供衬底，并且在衬底上形成多晶硅层。 栅极结构和非本征基极结构形成在多晶硅层中。 多个触点通过层间介质层形成到CMOS晶体管和异质结双极晶体管。

公开(公告)号：US20050101096A1

公开(公告)日：2005-05-12

申请号：US10703284

申请日：2003-11-06

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。