发明授权
US5903499A Method to erase a flash EEPROM using negative gate source erase followed
by a high negative gate erase
失效
使用负栅极源擦除后跟高负栅极擦除擦除闪存EEPROM的方法
- 专利标题: Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase
- 专利标题(中): 使用负栅极源擦除后跟高负栅极擦除擦除闪存EEPROM的方法
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申请号: US928227申请日: 1997-09-12
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公开(公告)号: US5903499A公开(公告)日: 1999-05-11
- 发明人: Kuo-Reay Peng , Jian-Hsing Lee , Juang-Ke Yeh , Ming-Chou Ho
- 申请人: Kuo-Reay Peng , Jian-Hsing Lee , Juang-Ke Yeh , Ming-Chou Ho
- 申请人地址: TWX Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TWX Hsin-Chu
- 主分类号: G11C16/14
- IPC分类号: G11C16/14 ; G11C16/04
摘要:
A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.
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