The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a detection circuit for detecting whether or not a displacement from a branch instruction to a branch target instruction is a specific displacement on the basis of branch displacement information that the concerned branch instruction holds. The instruction prefetch buffer clears an instruction already prefetched when the detection circuit detects that the displacement is not the specific displacement and outputs a branch target instruction newly fetched to the CPU, and outputs a branch target instruction already prefetched to the CPU when the detection circuit detects that the displacement is the specific displacement. Thus, the date processor fetches a branch target instruction within a certain range from the instruction prefetch buffer at a high speed without adding the nullifying bit on the instruction code.