发明授权
- 专利标题: Fully digital clock synthesizer
- 专利标题(中): 全数字时钟合成器
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申请号: US825082申请日: 1997-03-27
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公开(公告)号: US5920211A公开(公告)日: 1999-07-06
- 发明人: Michael B. Anderson , Gregory A. Tabor
- 申请人: Michael B. Anderson , Gregory A. Tabor
- 申请人地址: CA Milpitas
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 当前专利权人地址: CA Milpitas
- 主分类号: G06F11/36
- IPC分类号: G06F11/36 ; H03K5/00 ; H03B19/00 ; H03K3/017
摘要:
A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.
公开/授权文献
- US5264754A Spark plug 公开/授权日:1993-11-23