发明授权
- 专利标题: Clock timing recovery methods and circuits
- 专利标题(中): 时钟定时恢复方法和电路
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申请号: US897452申请日: 1997-07-22
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公开(公告)号: US5920220A公开(公告)日: 1999-07-06
- 发明人: Toshiaki Takao , Yoshifumi Suzuki , Tadashi Shirato
- 申请人: Toshiaki Takao , Yoshifumi Suzuki , Tadashi Shirato
- 申请人地址: JPX Tokyo
- 专利权人: Nippon Telegraph and Telephone Corporation
- 当前专利权人: Nippon Telegraph and Telephone Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX8-192293 19960722; JPX9-025429 19970207; JPX9-106261 19970423
- 主分类号: H04L7/00
- IPC分类号: H04L7/00 ; H04L7/02 ; H04L7/033 ; H04L7/04 ; H03H3/00
摘要:
A clock timing recovery circuit for recovering the clock timing from a baseband signal obtained by detection of a received signal. The clock timing is rapidly established using a clock signal which has been phase-shifted from the desired clock timing to sample the baseband signal, and by obtaining the optimum phase from the sampled signal obtained as a result. A clock-timing recovery circuit according to this invention does not require oversampling and provides easy optimization of circuit constants.
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