A dither circuit and method for reproducing a multicolor image includes a latch having input terminals for 8 input data bits and clock signal, and output terminals for six high bits and two low bits of the input-data bits; a dither timing generator having input terminals for a horizontal sync signal, a vertical sync signal and a clock signal and output terminals for a first dither timing bit and the second dither timing bit, wherein the first dither timing bit is toggled according to each cycle of the horizontal sync signal and the second dither timing bit is toggled according to each cycle of the vertical sync signal; a dither data controlierhaving input terminals for the two low bits, the first and the second dither timing bits and an output terminal for applying four dither data bits generated using the two low bits and the first and the second dither timing bits sequentially; and an adder having an input terminal for the dither data bit and six high bits, and output terminals for six output data bits.