发明授权
US5926037A Buffer circuit which transfers data held in a first latch circuit to a
second latch circuit
失效
将保持在第一锁存电路中的数据传送到第二锁存电路的缓冲电路
- 专利标题: Buffer circuit which transfers data held in a first latch circuit to a second latch circuit
- 专利标题(中): 将保持在第一锁存电路中的数据传送到第二锁存电路的缓冲电路
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申请号: US890619申请日: 1997-07-09
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公开(公告)号: US5926037A公开(公告)日: 1999-07-20
- 发明人: Fumiki Sato , Kouichi Fujita
- 申请人: Fumiki Sato , Kouichi Fujita
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX9-048213 19970303
- 主分类号: G11C11/417
- IPC分类号: G11C11/417 ; G11C19/00 ; H03K3/037 ; H03K3/356 ; H03K19/0175 ; G11C7/00 ; H03K19/094
摘要:
A buffer circuit which can solve a problem of a conventional buffer circuit in that high speed data transfer is hindered because of parasitic capacitance of signal lines, which has an affect on the discharge time of inverters in a latch circuit of the buffer circuit, when the buffer circuit changes its state from a first term (non-transfer mode) to a second term (transfer mode). The buffer circuit solves this problem by pouring a current, which flows thereinto from a first signal line, into ground through a first PMOS transistor, a first NMOS transistor and a third NMOS transistor, and by pouring a current, which flows thereinto from a second signal line, into the ground through a second PMOS transistor, a second NMOS transistor and the third NMOS transistor.
公开/授权文献
- US4706914A Attaching assembly 公开/授权日:1987-11-17
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