A method of manufacturing a complementary MOS device, comprising the steps of:(a) forming a gate insulating film on one major surface of a semiconductor substrate;(b) forming a first amorphous silicon film on said gate insulating film;(c) forming an oxide film having a thickness of about 1 nm on a surface of said first amorphous silicon film;(d) forming a second amorphous silicon film on said oxide film;(e) annealing said first and second amorphous silicon films to crystalize said first and second amorphous silicon films;(f) forming said first amorphous silicon film and said second amorphous silicon film into gate electrodes and simultaneously ion-implanting an n-type impurity into nMOSFET regions and a p-type impurity into pMOSFET regions; and(g) activating said n- and p-type impurities by the rapid thermal annealing.