发明授权
- 专利标题： Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer
- 专利标题（中）： 在半导体晶片的边缘排除处，防止在暴露表面上电镀铜的方法
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申请号： US854735申请日： 1997-05-12
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公开(公告)号： US5933758A公开(公告)日： 1999-08-03
- 发明人: Ajay Jain
- 申请人： Ajay Jain
- 申请人地址： IL Schaumburg
- 专利权人： Motorola, Inc.
- 当前专利权人： Motorola, Inc.
- 当前专利权人地址： IL Schaumburg
- 主分类号： C25D7/12
- IPC分类号： C25D7/12 ; H01L21/288 ; H01L21/768 ; H01L21/48 ; H01L21/283
摘要：
A method for forming a copper interconnect (54) begins by depositing a barrier layer (48). An intermediate layer (50) is formed over the barrier layer (48) by exposing the barrier layer (48) to a plasma silane environment. The layer (50) is conductive when deposited so that contact resistance is not affected. The layer (50) is insitu covered with a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20) thereby exposing a portion (50a) of the layer (50). This portion (50a) will natively oxidize in a room ambient to form a copper electroplating prevention barrier whereby copper will not electroplate in the region (20). Therefore, the region (50a) prevents barrier-to-copper interfaces to avoid delamination of the copper while preserving the edge exclusion region desired for copper electroplating.
公开/授权文献
- US4639383A Method and apparatus for coating particulate granules 公开/授权日：1987-01-27
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