公开(公告)号：US12227865B2

公开(公告)日：2025-02-18

申请号：US17872366

申请日：2022-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Che-Min Lin ,  Hung-San Lu ,  Chao-Lung Chen ,  Chao Yuan Chang ,  Chun-An Kung ,  Chin-Hsin Hsiao ,  Wen-Chun Hou ,  Szu-Hung Yang ,  Ping-Ching Jiang

IPC: C25D17/00 ,  C25D7/12 ,  H01L21/288

Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

公开(公告)号：US12224234B2

公开(公告)日：2025-02-11

申请号：US17629358

申请日：2021-03-15

Applicant: Beijing BOE Technology Development Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hu Meng

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/288 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/56

Abstract: A manufacturing method of a metal grid includes: providing a base substrate; forming a pattern including a first dielectric layer on the base substrate through a patterning process such that the first dielectric layer has a first groove in a lattice shape; forming a second dielectric layer on a side of the first dielectric layer away from the base substrate such that the second dielectric layer is deposited at least on a sidewall of the first groove to form a second groove in a lattice shape; and forming a metal material in the second groove, and removing at least a part of a material of the second dielectric layer such that an orthographic projection of the part of the material of the second dielectric layer on the base substrate does not overlap with an orthographic projection of the metal material on the base substrate, to form a metal grid.

公开(公告)号：US20250038004A1

公开(公告)日：2025-01-30

申请号：US18782040

申请日：2024-07-24

Applicant: The Hong Kong University of Science and Technology

Inventor： Sen YANG ,  Zeying CHEN ,  Wing Ki LO ,  Ning WANG

IPC: H01L21/288 ,  H01L29/16 ,  H01L29/24 ,  H01L29/45 ,  H01L29/772

Abstract: A method for a photon induced conductive material deposition on a substrate is provided. The method includes steps as follows: preparing a first solution comprising metalate, metal ions, or combinations thereof; preparing a first suspension comprising nanoparticles, a light sensitive reducing agent, an electron providing solvent, or combinations thereof; mixing the first solution and the first suspension to form a first reagent on a first substrate; and emitting a light beam provided by a light source and focusing the same onto the first reagent kept on a first region of the first substrate, so as to form a mechanically rigid conductive deposition in contact with the first substrate in a focus point of the light source, wherein the first substrate has a second region exposed to surrounding gas or an air environment.

公开(公告)号：US12148658B2

公开(公告)日：2024-11-19

申请号：US18074525

申请日：2022-12-05

Applicant: InnoLux Corporation

Inventor： Cheng-Chi Wang ,  Yeong-E Chen ,  Cheng-En Cheng

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/288 ,  H01L21/48 ,  H01L21/66 ,  H01L21/683

Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; a photoresist coating process; a development process; an etching process; an exposure process; a metal plating process; and a polishing process, wherein the photoresist coating process, the development process, the etching process, the exposure process, the metal plating process and the polishing process respectively have a maximum optimized process area, and a smallest one of the maximum optimized process areas is selected as the basic working area.

公开(公告)号：US20240309511A1

公开(公告)日：2024-09-19

申请号：US18263435

申请日：2022-01-20

Applicant: Tokyo Electron Limited

Inventor： Takeshi Nagao ,  Yuichiro Inatomi ,  Kazutoshi Iwai

IPC: C23C18/16 ,  C23C18/40 ,  H01L21/288 ,  H01L21/768

CPC classification number: C23C18/1658 ,  C23C18/163 ,  C23C18/1632 ,  C23C18/1675 ,  C23C18/40 ,  H01L21/288 ,  H01L21/76838

Abstract: A plating method includes a preparation process; a first plating process; and a second plating process. In the preparation process, a substrate W having a seed layer 132 of cobalt or a cobalt alloy formed in a recess is prepared. In the first plating process, a displacement plating processing is performed on the substrate W to replace a surface layer of the seed layer 132 with copper by using a first plating liquid L1 containing a copper ion. In the second plating process, after the first plating process, a reduction plating processing is performed on the recess of the substrate W by using a second plating liquid L2 containing a copper ion and a reducing agent.

公开(公告)号：US20240297106A1

公开(公告)日：2024-09-05

申请号：US18177953

申请日：2023-03-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L27/146 ,  H01L29/08 ,  H02M3/158

CPC classification number: H01L23/49827 ,  H01L21/02035 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/67069 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/26 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/4822 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/562 ,  H01L24/00 ,  H01L24/05 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/14 ,  H01L27/14683 ,  H01L29/0847 ,  H02M3/158 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/49816 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3511

Abstract: A through-substrate via structure includes a conductive via structure including trench portions at a first major surface of a substrate and extending to a first distance. A first insulating structure is over sidewalls of the trench portions, and a conductive material is over the first insulating structure. A recessed region extends from a second major surface of the substrate to a second distance greater than the first distance and laterally overlaps and interfaces both trench portions. A second insulating structure includes a first portion within the recessed region and a second portion adjacent to the second major surface outside of the recessed region, which includes an outer surface overlapping the second major surface outside of the recessed region. A first conductive region includes a proximate end coupled to the conductive material through openings in the first portion, and an opposite distal that is outward from the second portion.

公开(公告)号：US20240297068A1

公开(公告)日：2024-09-05

申请号：US18663364

申请日：2024-05-14

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sony Varghese ,  John A. Smythe ,  Hyun Sik Kim

IPC: H01L21/762 ,  B29C35/08 ,  B29C41/08 ,  B29K83/00 ,  B32B3/26 ,  H01L21/02 ,  H01L21/288 ,  H01L21/32 ,  H01L21/67 ,  H01L21/768

CPC classification number: H01L21/7624 ,  B29C41/08 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/0226 ,  H01L21/02288 ,  H01L21/02631 ,  H01L21/288 ,  H01L21/76232 ,  H01L21/76837 ,  H01L21/76877 ,  B29C2035/0827 ,  B29K2083/00 ,  B32B3/266 ,  H01L21/32 ,  H01L21/6715

Abstract: Some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. Some embodiments include methods of filling openings that extend into a semiconductor construction. The methods may include, for example, printing the material into the openings or pressing the material into the openings. The construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. In some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.

公开(公告)号：US12080648B2

公开(公告)日：2024-09-03

申请号：US17517472

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Yang Cao ,  Akm Shaestagir Chowdhury ,  Jeff Grunes

IPC: H01L23/532 ,  H01L21/288 ,  H01L21/768

CPC classification number: H01L23/53261 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conducting alloys comprising cobalt, tungsten, and boron and conducting alloys comprising nickel, tungsten, and boron are described. These alloys can, for example, be used to form metal interconnects, can be used as liner layers for traditional copper or copper alloy interconnects, and can act as capping layers. The cobalt-tungsten and nickel-tungsten alloys can be deposited using electroless processes.

公开(公告)号：US12051617B2

公开(公告)日：2024-07-30

申请号：US17816051

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Min Han Hsu ,  Chun-Chang Chen ,  Jung-Chih Tsao

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/285 ,  H01L21/288 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53228

Abstract: A method includes depositing a metallic hardmask over a dielectric layer. The method further includes etching a metallic hardmask opening in the metallic hardmask to expose a top surface of the dielectric layer. Th method further includes modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask. The method further includes depositing a conductive material in the metallic hardmask opening.

公开(公告)号：US20240250036A1

公开(公告)日：2024-07-25

申请号：US18592850

申请日：2024-03-01

Applicant: Taiwan Semicoductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Tseng ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/538 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L21/288 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L21/3212 ,  H01L23/3128 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/24137 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: In an embodiment, a device includes: an integrated circuit die; a through via adjacent the integrated circuit die; a molding compound encapsulating the integrated circuit die and the through via; and a redistribution structure including: a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line.