发明授权
US5938777A Cycle list based bus cycle resolution checking in a bus bridge
verification system
失效
在总线桥接验证系统中基于周期列表的总线周期分辨率检查
- 专利标题: Cycle list based bus cycle resolution checking in a bus bridge verification system
- 专利标题(中): 在总线桥接验证系统中基于周期列表的总线周期分辨率检查
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申请号: US904191申请日: 1997-07-31
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公开(公告)号: US5938777A公开(公告)日: 1999-08-17
- 发明人: Hamilton B. Carter
- 申请人: Hamilton B. Carter
- 申请人地址: CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: CA Sunnyvale
- 主分类号: G06F11/267
- IPC分类号: G06F11/267 ; G06F11/00
摘要:
In a computer system having a bus bridge connecting a plurality of system buses, a cycle list based bus cycle resolution checking system and method have been disclosed. Each bus in the system is treated as an individual, persistent object. Various bus cycles on system buses are also modeled as objects. Each bus object is configured to detect an initiation of a corresponding bus cycle. An initiator cycle list for holding bus cycles initiated by bus masters, and a target cycle list for storing bus cycles sent to bus targets are also created. Each cycle list itself is treated as an object. These cycle lists combinedly interact with a bus object to verify resolution of an initiator bus cycle. A stimulator object may provide a bus stimulus to each bus object as well as to each cycle list. The stimulator object may read said bus stimulus from a stimulus file of real or simulated buses. In such a case, bus bridge performance and functionality can be tested through externally simulated bus signals. Each bus object may instantiate a corresponding bus cycle state machine object upon detection of an initiated bus cycle and store it in the corresponding cycle list. Finally, the initiator cycle list may pass a pointer from each bus cycle state machine object in the target list to each initiator bus cycle state machine object to verify target data resolution for an initiator cycle.
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