公开(公告)号：US6154801A

公开(公告)日：2000-11-28

申请号：US161342

申请日：1998-09-25

申请人： Mike Lowe ,  Mark LaVine ,  Jelena Ilic ,  Paul Berndt ,  Tahsin Askar ,  Enrique Rendon ,  Hamilton B. Carter

发明人： Mike Lowe ,  Mark LaVine ,  Jelena Ilic ,  Paul Berndt ,  Tahsin Askar ,  Enrique Rendon ,  Hamilton B. Carter

IPC分类号： G06F11/267 ,  G06F13/40 ,  G06F17/50 ,  G06F13/368

CPC分类号： G06F13/4027 ,  G06F11/221 ,  G06F17/5022

摘要： A verification system and method for verifying operation of an HDL (Hardware Description Language) design of a computer system component are disclosed. The computer system is configured to interface between a first bus and second bus. During verification, a simulated model of the HDL design is coupled to a simulated first bus and a simulated second bus. A designated stimulus is applied to the simulated model through the simulated first bus. A stimulus file stored in the computer system memory is configured to specify the designated stimulus to be applied. In response to the designated stimulus, the simulated model initiates bus cycles on the simulated second bus. A transaction checker is provided in the computer system memory to receive information relating to these bus cycles from said simulated second bus. By employing two different busses--one to apply a stimulus and the other to resolve the bus cycle through transaction checking--an effective decoupling of test stimulus from the checking environment is achieved. Due to decoupling, the test environment can be made more robust, and can be used to generate random responses, remap memory, inject errors into data streams etc.

摘要翻译： 公开了一种用于验证计算机系统组件的HDL（硬件描述语言）设计的操作的验证系统和方法。 计算机系统被配置为在第一总线和第二总线之间进行接口。 在验证期间，HDL设计的模拟模型耦合到模拟的第一总线和模拟的第二总线。 通过模拟的第一条总线将指定的刺激应用于模拟模型。 存储在计算机系统存储器中的激励文件被配置为指定要应用的指定的刺激。 响应于指定的刺激，模拟模型在模拟的第二总线上启动总线周期。 在计算机系统存储器中提供事务检查器，以从所述模拟的第二总线接收与这些总线周期有关的信息。 通过使用两个不同的总线 - 一个应用刺激，另一个通过事务检查来解决总线周期 - 实现了测试刺激与检查环境的有效解耦。 由于解耦，测试环境可以更加鲁棒，可用于生成随机响应，重映射存储器，将错误注入数据流等。

公开(公告)号：US5996050A

公开(公告)日：1999-11-30

申请号：US904434

申请日：1997-07-31

申请人： Hamilton B. Carter ,  William M. Lowe

发明人： Hamilton B. Carter ,  William M. Lowe

IPC分类号： G06F12/08

CPC分类号： G06F12/0835 ,  G06F11/221 ,  G06F2212/1032

摘要： A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address and data contained in each cache line and a flag indicating the state of the cache line (e.g., MESI state, or other cache coherency protocol state) is utilized. In addition, the cache model object also holds a dynamically allocated list (the cycle list) of bus cycles. This list is used to store pointers to non-cache bus cycles initiated in the multi-bus system. Cache bus cycles can update the state of the cache model object and can also instruct the cache model to perform coherency tests on pending non-cache bus cycles in the cycle list. When all protocol tests for a non-cache bus cycle have been successfully completed, no further coherency tests are performed on that bus cycle. Cache master verification is also achieved by polling the cache model to determine source of target resolution cycles for a bus cycle initiated by bus masters. Thus, cache coherency and cache controller operations are efficiently checked.

摘要翻译： 公开了一种提供高速缓存一致性错误检测的方法，以及高速缓存主机对低效高速缓存使用的检测。 使用具有用于包含在每个高速缓存行中的地址和数据的高速缓存的模型以及指示高速缓存行的状态的标志（例如，MESI状态或其他高速缓存一致性协议状态）。 另外，缓存模型对象还保存了一个动态分配的总线周期列表（循环列表）。 该列表用于存储在多总线系统中启动的非高速缓存总线周期的指针。 缓存总线周期可以更新缓存模型对象的状态，并且还可以指示高速缓存模型对循环列表中的未缓存的非高速缓存总线周期执行一致性测试。 当非高速缓存总线周期的所有协议测试都已经成功完成时，在该总线周期内不进行进一步的一致性测试。 高速缓存主验证也通过轮询高速缓存模型来确定由总线主机启动的总线周期的目标分辨率周期的来源。 因此，高效地检查高速缓存一致性和高速缓存控制器操作。

公开(公告)号：US5961625A

公开(公告)日：1999-10-05

申请号：US904192

申请日：1997-07-31

申请人： Hamilton B. Carter

发明人： Hamilton B. Carter

IPC分类号： G06F11/267 ,  G06F11/30 ,  G06F11/34 ,  G06F13/00

CPC分类号： G06F11/221 ,  G06F11/3027 ,  G06F11/3041 ,  G06F11/3055 ,  G06F11/349

摘要： A system for and a method of monitoring the current state of a bus bridge in a device independent manner are disclosed. In a computer system having a bus bridge connecting a plurality of system buses, a bus bridge model object is created with storage space allocated for each of the bus bridge's configuration registers. A CPU write cycle state machine object may send bus cycles intended for the bus bridge to the bus bridge model also. Using the data from these cycles, the model updates its registers accordingly. Thus, the current state of the bus bridge is always known. In one embodiment, bus cycle state machine objects can also poll the bus bridge model object to determine if a bus cycle address is remapped by the bus bridge. Various bus objects, through their state machines, may also poll the bus bridge model for pertinent information. Hence, false failures because of a lack of knowledge of the state of the bus bridge can be eliminated and a tighter verification of bus bridge operations can be accomplished.

摘要翻译： 公开了以设备独立的方式监视总线桥的当前状态的系统和方法。 在具有连接多个系统总线的总线桥的计算机系统中，创建总线桥模型对象，其中为每个总线桥的配置寄存器分配存储空间。 CPU写周期状态机对象也可以将用于总线桥的总线周期发送到总线桥模型。 使用这些周期的数据，模型会相应地更新其寄存器。 因此，总线桥的当前状态总是已知的。 在一个实施例中，总线周期状态机对象还可以轮询总线桥模型对象以确定总线周期地址是否被总线桥重新映射。 各种巴士对象，通过他们的状态机，也可以轮询公交车桥模型的相关信息。 因此，可以消除由于缺乏对公共汽车桥的状态的了解而造成的错误故障，并且可以实现对总线桥操作的更严格的验证。

公开(公告)号：US5941971A

公开(公告)日：1999-08-24

申请号：US904195

申请日：1997-07-31

申请人： Hamilton B. Carter

发明人： Hamilton B. Carter

IPC分类号： G06F11/267 ,  G06F13/38 ,  G06F13/42

CPC分类号： G06F11/221

摘要： A method to correctly resolve combined data cycles in a bus bridge's posted write buffer is described. In a computer system with a bus bridge connecting a plurality of system buses, a state machine model is created for each bus in the system. A bus cycle state machine object corresponding to an initiated bus cycle is instantiated and stored in at least one of a plurality of cycle list objects. The combine cycle list stores combinable bus cycles and has number of entries equal to the number of entries in the posted write buffer. A pointer may be placed in the combine list upon creation of each combinable bus cycle. For each combinable cycle stored in it, the initiator cycle list searches the combine list for a cycle with an identical address and byte enable, but a later clock cycle number. This later cycle is matched its data with an appropriate target cycle in the target cycle list. Upon finding the data match, the initiator cycle list resolves the combinable initiator cycle. Thus, false failures due to byte collapsing can be eliminated.

摘要翻译： 描述了一种在总线桥的写入缓冲器中正确解析组合数据周期的方法。 在具有连接多个系统总线的总线桥的计算机系统中，为系统中的每个总线创建状态机模型。 对应于发起的总线周期的总线周期状态机对象被实例化并存储在多个循环列表对象中的至少一个中。 组合循环列表存储可组合的总线周期，并且具有等于发布的写缓冲器中的条目数的条目数。 创建每个可组合的总线周期后，指针可以放在组合列表中。 对于存储在其中的每个可组合循环，启动器周期列表搜索组合列表中具有相同地址和字节使能的周期，但是稍后的时钟周期数。 该后续周期与其数据与目标周期列表中的适当目标周期相匹配。 在找到数据匹配后，启动器周期列表可以解决可组合的启动器周期。 因此，可以消除由于字节折叠引起的错误故障。

公开(公告)号：US5938777A

公开(公告)日：1999-08-17

申请号：US904191

申请日：1997-07-31

申请人： Hamilton B. Carter

发明人： Hamilton B. Carter

IPC分类号： G06F11/267 ,  G06F11/00

CPC分类号： G06F11/221

摘要： In a computer system having a bus bridge connecting a plurality of system buses, a cycle list based bus cycle resolution checking system and method have been disclosed. Each bus in the system is treated as an individual, persistent object. Various bus cycles on system buses are also modeled as objects. Each bus object is configured to detect an initiation of a corresponding bus cycle. An initiator cycle list for holding bus cycles initiated by bus masters, and a target cycle list for storing bus cycles sent to bus targets are also created. Each cycle list itself is treated as an object. These cycle lists combinedly interact with a bus object to verify resolution of an initiator bus cycle. A stimulator object may provide a bus stimulus to each bus object as well as to each cycle list. The stimulator object may read said bus stimulus from a stimulus file of real or simulated buses. In such a case, bus bridge performance and functionality can be tested through externally simulated bus signals. Each bus object may instantiate a corresponding bus cycle state machine object upon detection of an initiated bus cycle and store it in the corresponding cycle list. Finally, the initiator cycle list may pass a pointer from each bus cycle state machine object in the target list to each initiator bus cycle state machine object to verify target data resolution for an initiator cycle.

摘要翻译： 在具有连接多个系统总线的总线桥的计算机系统中，已经公开了一种基于循环列表的总线周期分辨率检查系统和方法。 系统中的每个总线被视为一个单独的持久对象。 系统总线上的各种总线周期也被建模为对象。 每个总线对象被配置为检测相应总线周期的启动。 用于保持由总线主机发起的总线周期的发起者周期列表，以及用于存储发送到总线目标的总线周期的目标周期列表。 每个循环列表本身被视为一个对象。 这些循环列表组合地与总线对象交互以验证启动器总线周期的分辨率。 刺激器对象可以向每个总线对象以及每个周期列表提供总线刺激。 刺激器对象可以从真实或模拟总线的刺激文件读取所述总线刺激。 在这种情况下，可以通过外部模拟总线信号来测试总线桥的性能和功能。 每个总线对象可以在检测到启动的总线周期时实例化相应的总线周期状态机对象，并将其存储在相应的周期列表中。 最后，发起者周期列表可以将目标列表中的每个总线周期状态机对象的指针传递给每个启动器总线周期状态机对象，以验证发起者周期的目标数据分辨率。

公开(公告)号：US5996034A

公开(公告)日：1999-11-30

申请号：US949885

申请日：1997-10-14

申请人： Hamilton B. Carter

发明人： Hamilton B. Carter

IPC分类号： G06F12/08 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4217 ,  G06F12/0835

摘要： A transaction checking system and method to verify bus bridge designs in multi-master bus systems. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine objects and transition their states according to bus signals. The bus cycle state machines provide a means of persistent storage for other verification tasks. A bus bridge model may store a copy of each configuration register for the bus bridge, thereby monitoring current state of the bus bridge. False failures due to data merging, data collapsing and address remapping are avoided. A cache model and a cycle-based messaging system provide verification of proper cache master operation. Cache coherency errors may also be detected. A statistics keeping object may be created to monitor and store all pertinent performance information for the bus bridge. The transaction checking system may monitor the state of the bus bridge in a device independent manner and with tighter verification. The cycle-based approach to verification of internal states of a bus bridge results in a sound resolution of bus cycles with a better predictability of possible failures. Bus monitors may be employed along with the bus bridge model object to determine the values of the bus bridge configuration registers. This allows timing and other protocol related functionality of a system bus attached to the bus bridge to be verified without restricting the bus monitor to a specific bus bridge design (e.g., without requiring the bus monitors to maintain the net list names for the various configuration registers identified by the hardware description language representation of the bus bridge). Additionally, future bus bridge designs can also be tested in a device independent manner.

摘要翻译： 一种用于在多主总线系统中验证总线桥设计的事务检查系统和方法。 为系统中的每个总线创建状态机模型。 启动器周期列表和目标周期列表存储对应的总线周期状态机对象，并根据总线信号转换其状态。 总线周期状态机为其他验证任务提供持久存储的手段。 总线桥模型可以存储用于总线桥的每个配置寄存器的副本，从而监视总线桥的当前状态。 避免了由于数据合并，数据崩溃和地址重映射引起的错误故障。 缓存模型和基于循环的消息传递系统提供正确的高速缓存主控操作的验证。 还可以检测到缓存一致性错误。 可以创建统计信息对象来监视和存储总线桥的所有相关性能信息。 事务检查系统可以以独立于设备的方式和更严格的验证来监视总线桥的状态。 基于循环的验证总线桥内部状态的方法可以有效地解决总线周期，从而更好地预测可能发生的故障。 总线监视器可以与总线桥模型对象一起使用，以确定总线桥配置寄存器的值。 这允许连接到总线桥的系统总线的定时和其他协议相关功能被验证，而不必将总线监视器限制到特定的总线桥设计（例如，不需要总线监视器来维护各种配置寄存器的网络列表名称 由总线桥的硬件描述语言表示来识别）。 此外，未来的总线桥设计也可以以独立于设备的方式进行测试。

公开(公告)号：US5963722A

公开(公告)日：1999-10-05

申请号：US904190

申请日：1997-07-31

申请人： Hamilton B. Carter

发明人： Hamilton B. Carter

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： A method to track bus cycle data with byte granularity in a computer system with a bus bridge connecting a plurality of system buses is disclosed. The method eliminates false failures due to data merging performed by the bus bridge to enhance performance. A state machine model is created for each bus in the system. Each bus model is responsible for creating a bus cycle state machine object upon detecting an initiation of a corresponding bus cycle and storing it in an initiator or a target cycle list as the case may be. The bus cycle state machines are transitioned according to bus signals until a final state is reached--i.e. a state indicating that the bus protocol for the corresponding cycle was properly completed and only resolution of target data is pending. In this final state, initiator cycles compare their data bytes with those of target cycles only when they have common byte enables. These common byte enables may be deasserted upon finding of matching data bytes. Each initiator cycle remains in its final state until each byte of its data is accounted for.

摘要翻译： 公开了一种在具有连接多个系统总线的总线桥的计算机系统中跟踪具有字节粒度的总线周期数据的方法。 该方法消除了由总线桥执行的数据合并以提高性能的错误故障。 为系统中的每个总线创建状态机模型。 每个总线模型负责在检测到相应总线周期的启动时创建总线周期状态机对象，并将其存储在发起者或目标周期列表中（视具体情况而定）。 总线周期状态机根据总线信号进行转换，直到达到最终状态。 指示相应周期的总线协议正确完成并且仅目标数据的分辨率待定的状态。 在这种最终状态下，只有当它们具有公共字节使能时，启动器周期才将其数据字节与目标周期的字节进行比较。 这些公共字节使能可能在找到匹配的数据字节时被取消置位。 每个发起者周期保持在其最终状态，直到其数据的每个字节被考虑为止。

公开(公告)号：US06745375B1

公开(公告)日：2004-06-01

申请号：US09252174

申请日：1999-02-18

申请人： Hamilton B. Carter

发明人： Hamilton B. Carter

IPC分类号： G06F945

CPC分类号： G06F17/5022

摘要： The computational load of using a sequencer system and the memory allocation requirements demanded for sequencer operation are reduced in operation with functional models that do not require the services of a sequencer. The computational overhead introduced by the sequencer is reduced, and memory resources for a sequencer are diminished. Functional models that do not require sequencing are created with the same framework as functional models that do require sequencing, while eliminating the sequencer's computational overhead for functional models that do not require sequencing, and allowing functional models that to not require sequencing to be created without allocating the memory required to support the sequencer. Further, both sequenced and un-sequenced functional models coexist in the same sequenced verification framework, permitting the un-sequenced functional models to avoid the computational and memory allocation overhead otherwise incurred by the sequencer.

摘要翻译： 使用定序器系统的计算负载和要求定序器操作的存储器分配要求在不需要定序器服务的功能模型的情况下被减少。 由定序器引入的计算开销减少，并且定序器的存储器资源减少。 不需要排序的功能模型使用与需要排序的功能模型相同的框架创建，同时消除不需要排序的功能模型的定序器的计算开销，并允许在不分配的情况下创建不需要排序的功能模型 支持音序器所需的内存。 此外，序列和未排序的功能模型在相同的排序验证框架中共存，允许未排序的功能模型避免由定序器引起的计算和存储器分配开销。

公开(公告)号：US5930482A

公开(公告)日：1999-07-27

申请号：US904504

申请日：1997-07-31

申请人： Hamilton B. Carter ,  William M. Lowe

发明人： Hamilton B. Carter ,  William M. Lowe

IPC分类号： G06F11/267 ,  G06F13/40 ,  G06F17/50 ,  G06F13/00

CPC分类号： G06F11/221 ,  G06F13/4027 ,  G06F17/5022

摘要： A transaction checking system and method to verify bus bridges in multi-master bus systems are described. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine objects and transition their states according to bus signals. The bus cycle state machines provide a mechanism of persistent storage for other verification tasks. A bus bridge model may store a copy of each configuration register for the bus bridge, thereby monitoring current state of the bus bridge. False failures due to data merging, data collapsing and address remapping are avoided. A cache model and a cycle-based messaging system provide verification of proper cache master operation. Cache coherency errors may also be detected. A statistics keeping object may be created to monitor and store all pertinent performance information for the bus bridge. The transaction checking system may monitor the state of the bus bridge in a device independent manner and with tighter verification. The cycle-based approach to verification of internal states of a bus bridge results in a sound resolution of bus cycles with a better predictability of possible failures.

摘要翻译： 描述了一种用于验证多主总线系统中总线桥的事务检查系统和方法。 为系统中的每个总线创建状态机模型。 启动器周期列表和目标周期列表存储对应的总线周期状态机对象，并根据总线信号转换其状态。 总线周期状态机为其他验证任务提供持久存储的机制。 总线桥模型可以存储用于总线桥的每个配置寄存器的副本，从而监视总线桥的当前状态。 避免了由于数据合并，数据崩溃和地址重映射引起的错误故障。 缓存模型和基于循环的消息传递系统提供正确的高速缓存主控操作的验证。 还可以检测到缓存一致性错误。 可以创建统计信息对象来监视和存储总线桥的所有相关性能信息。 事务检查系统可以以独立于设备的方式和更严格的验证来监视总线桥的状态。 基于循环的验证总线桥内部状态的方法可以有效地解决总线周期，从而更好地预测可能发生的故障。

公开(公告)号：US5960457A

公开(公告)日：1999-09-28

申请号：US846651

申请日：1997-05-01

申请人： Joseph Skrovan ,  Royce K. Presley ,  Hamilton B. Carter

发明人： Joseph Skrovan ,  Royce K. Presley ,  Hamilton B. Carter

IPC分类号： G06F12/08 ,  G11C29/02 ,  G11C29/10 ,  G11C29/50 ,  G06F12/00

CPC分类号： G11C29/50012 ,  G06F12/0831 ,  G11C29/02 ,  G11C29/50 ,  G06F2212/1032 ,  G11C15/00 ,  G11C29/10

摘要： A test methodology for a cache memory subsystem includes setting a test unit to initiate a snoop cycle on a local bus upon lapse of a predetermined delay. The predetermined delay is initially set to a very short delay or a zero delay. The snoop cycle to be executed may take the form of an inquire cycle to a predetermined memory address. The test unit is further set or programmed to begin monitoring the local bus for certain activity including activity which is indicative of whether the snoop cycle occurred. After programming the test unit, the processor core executes a memory operation associated with the address of the snoop cycle. This memory operation causes a cache line transition. At some point, either before, during or after effectuation of the memory operation, the snoop cycle is executed by the test unit in accordance with the predetermined delay. Upon completing the memory operation, a status register is read from the test unit to determine whether the snoop cycle has yet occurred. If the snoop cycle occurred prior to completing the memory operation, the predetermined delay is increased and the test is repeated for the increased delay. Prior to repeating the test, the cache line's coherency with external memory is checked for conformance with the cache protocol. Additionally, the test unit may further be programmed to detect an occurrence of certain external local bus signals generated by the cache memory subsystem, such as a signal indicating a hit to a cache line occurred, and a signal indicating that a hit to a modified line in the cache occurred. The test is repeated until it is determined that the snoop cycle has not occurred upon completion of the line fill instruction.

摘要翻译： 高速缓存存储器子系统的测试方法包括设置测试单元以在经过预定延迟时在局部总线上发起窥探周期。 预定的延迟最初被设置为非常短的延迟或零延迟。 要执行的侦听周期可以以查询周期的形式到预定的存储器地址。 测试单元进一步设置或编程为开始监视局部总线的某些活动，包括指示是否发生窥探周期的活动。 在对测试单元进行编程之后，处理器核心执行与窥探周期的地址相关联的存储器操作。 该存储器操作导致高速缓存行转换。 在某一时刻，在存储器操作之前，期间或之后，通过测试单元根据预定的延迟执行窥探周期。 在完成存储器操作时，从测试单元读取状态寄存器以确定窥探周期是否仍然发生。 如果在完成存储器操作之前发生探听周期，则增加预定延迟并且为了延长延迟重复测试。 在重复测试之前，检查缓存行与外部存储器的一致性是否符合缓存协议。 此外，测试单元还可以被编程为检测由高速缓存存储器子系统产生的某些外部局部总线信号的发生，例如指示发生高速缓存线的命中的信号，以及指示对修改的线的命中的信号 在缓存中发生。 重复该测试，直到确定在行填充指令完成后探测周期未发生。