发明授权
US5940606A Duty cycle controller for clock signal to synchronous SRAM on FPGA
失效
FPGA上同步SRAM时钟信号的占空比控制器
- 专利标题： Duty cycle controller for clock signal to synchronous SRAM on FPGA
- 专利标题（中）： FPGA上同步SRAM时钟信号的占空比控制器
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申请号： US20622申请日： 1998-02-09
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公开(公告)号： US5940606A公开(公告)日： 1999-08-17
- 发明人: Atul V. Ghia , Suresh M. Menon
- 申请人： Atul V. Ghia , Suresh M. Menon
- 申请人地址： CA Sunnyvale
- 专利权人： DynaChip Corporation
- 当前专利权人： DynaChip Corporation
- 当前专利权人地址： CA Sunnyvale
- 主分类号： G06F1/025
- IPC分类号： G06F1/025 ; G11C7/10 ; G11C7/22 ; G11C11/413 ; G06F1/04
摘要：
A duty cycle controller for generating proper control signals for an SRAM in an FPGA in the proper sequence and spaced at the proper times to guarantee proper operation of the SRAM regardless of the frequency of duty cycle of the clock selected by the user to synchronize and drive operations of the SRAM.