公开(公告)号：US5883852A

公开(公告)日：1999-03-16

申请号：US28956

申请日：1998-02-23

申请人： Atul V. Ghia ,  Paul Takao Sasaki

发明人： Atul V. Ghia ,  Paul Takao Sasaki

IPC分类号： G11C7/10 ,  G11C8/16 ,  G11C11/417 ,  G11C11/419 ,  H03K19/177 ,  G11C8/00 ,  G11C16/04

CPC分类号： H03K19/1776 ,  G11C11/417 ,  G11C11/419 ,  G11C7/1006 ,  G11C8/16

摘要： A configurable SRAM for a field programmable gate array. Two memory arrays each have a data input, a data output, a write enable input and port A and B address inputs. First and second address buses are selectively coupled to the port A and port B address inputs through multiplexers such that different configurations can be achieved. The multiplexers are controlled by a dual port/single port steering signal and a x1/x2 steering signal such that the following configurations can be achieved: 32 x1 dual port; 32 x1 single port and 16 x2 single port. In dual port configurations, simultaneous read and write operations to different cells can occur. In x2 configuration, each array is operated as an independent memory with its own address input, its own data output and its own data input. In x1 single port configuration, one data input line and one data output line and one address bus are shared between the two arrays, and an extra address bit is used to steer the write enable signals and the output multiplexer circuitry such the write enable signal reaches the proper array and the data output from the array being read reaches the shared output line.

摘要翻译： 用于现场可编程门阵列的可配置SRAM。 两个存储器阵列各自具有数据输入，数据输出，写使能输入和端口A和B地址输入。 第一和第二地址总线通​​过复用器选择性地耦合到端口A和端口B的地址输入，使得可以实现不同的配置。 多路复用器由双端口/单端口转向信号和x1 / x2转向信号控制，从而可以实现以下配置：32 x1双端口; 32 x1单端口和16 x2单端口。 在双端口配置中，可能会发生对不同单元的同时读和写操作。 在x2配置中，每个阵列都作为具有自己的地址输入，自己的数据输出和自己的数据输入的独立存储器运行。 在x1单端口配置中，两个阵列之间共享一个数据输入线和一个数据输出线和一个地址总线，另外一个额外的地址位用于引导写使能信号和输出多路复用器电路，使写使能信号达到 正确的数组和正在读取的阵列的数据输出到达共享输出行。

公开(公告)号：US06002268A

公开(公告)日：1999-12-14

申请号：US978691

申请日：1997-11-26

申请人： Paul Takao Sasaki ,  Madhukar Vora ,  Burnell G West

发明人： Paul Takao Sasaki ,  Madhukar Vora ,  Burnell G West

IPC分类号： H03K17/62 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1778 ,  H03K17/6257 ,  H03K17/6264 ,  H03K17/6285 ,  H03K17/6292 ,  H03K19/01759 ,  H03K19/1737 ,  H03K19/17704

摘要： An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit. Because of the substantially identical structure of each interface and the preservation of ratios between I/O cells, power and ground connections and open slots, larger or smaller core arrays may be accommodated by cutting and pasting additional interface circuits into the layout thereby substantially decreasing design, placement and layout time and time to market for introduction of new FPGAs in a family with larger core arrays. The regular repeatable structure of RIU's simplifies software development for products within the family and as such contributes to faster "time to market".

摘要翻译： 一种用于现场可编程门阵列的焊盘接口电路布局的接口电路，其具有多个I / O单元，每个I / O单元可被编程为输入或输出（或两者）和可编程连接矩阵，其提供可编程通道 在由逻辑块的核心阵列和被编程为输出的I / O单元产生的数据输出信号之间，并且在被编程为输入的I / O单元和进入核心阵列的数据输入导体之间提供可编程通道。 接口电路的结构基本相同，并且每个接口电路都包括足够数量的电源和接地连接，以向接口所具有的I / O单元的数量提供足够的电流。 每个接口电路还包括至少一个并且优选两个开放空间，导电路径可布置在该开放空间中，以将功率传递到核心阵列，或将专用信号传送到也位于集成电路上的核心以外的电路。 由于每个接口的结构基本相同，并且保持了I / O单元，电源和接地连接以及开放槽之间的比率，因此可以通过将附加的接口电路切割并粘贴到布局中来适应更大或更小的磁芯阵列，从而大大减少设计 ，放置和布局时间和上市时间，以便在具有较大核心阵列的家族中引入新的FPGA。 RIU的常规可重复结构简化了家庭产品的软件开发，因此有助于加快“上市时间”。

公开(公告)号：US5940606A

公开(公告)日：1999-08-17

申请号：US20622

申请日：1998-02-09

申请人： Atul V. Ghia ,  Suresh M. Menon

发明人： Atul V. Ghia ,  Suresh M. Menon

IPC分类号： G06F1/025 ,  G11C7/10 ,  G11C7/22 ,  G11C11/413 ,  G06F1/04

CPC分类号： G06F1/025 ,  G11C11/413 ,  G11C7/1072 ,  G11C7/22

摘要： A duty cycle controller for generating proper control signals for an SRAM in an FPGA in the proper sequence and spaced at the proper times to guarantee proper operation of the SRAM regardless of the frequency of duty cycle of the clock selected by the user to synchronize and drive operations of the SRAM.

摘要翻译： 一个占空比控制器，用于以合适的顺序产生适当序列中的SRAM的正确控制信号，并在适当的时间间隔，以保证SRAM的正常工作，无论用户选择的时钟占空比的频率如何同步和驱动 SRAM的操作。

公开(公告)号：US5668495A

公开(公告)日：1997-09-16

申请号：US639272

申请日：1996-04-23

申请人： Madhukar B. Vora ,  Burnell G. West

发明人： Madhukar B. Vora ,  Burnell G. West

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/00 ,  H03K17/62 ,  H03K19/086 ,  H03K19/173 ,  H03K17/60

CPC分类号： H03K17/6285 ,  H03K17/6257 ,  H03K19/1737

摘要： A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

摘要翻译： 适用于在高速数据通路中使用电流模式逻辑实现现场可编程门阵列的高速开关技术，以及高速数据通路外的CMOS转向逻辑，以实现高速开关逻辑和实现多路复用器，选择器和交叉开关功能 。 还公开了与高速开关逻辑兼容的高速射极跟随器逻辑，用于电平转换，缓冲和提供更多的电流吸收或源极容量。

公开(公告)号：US5654665A

公开(公告)日：1997-08-05

申请号：US444111

申请日：1995-05-18

申请人： Suresh M. Menon ,  Tsung Chuan Whang

发明人： Suresh M. Menon ,  Tsung Chuan Whang

IPC分类号： G05F3/20 ,  G05F3/26 ,  G05F3/02

CPC分类号： G05F3/205 ,  G05F3/267

摘要： A biasing system for a differential amplifier includes an NMOS current source and a gate bias voltage generator. The gate bias voltage generator produces a bias voltage VNCS to control the NMOS current source. The gate bias generator includes a reference current generator to produce a reference current relatively independent of supply voltage variations. A temperature compensator regulates the reference current to provide a temperature compensated current. A current mirror duplicates the temperature compensated current to a bias voltage generator. The bias voltage generator generates the bias voltage.

摘要翻译： 用于差分放大器的偏置系统包括NMOS电流源和栅极偏置电压发生器。 栅极偏置电压发生器产生偏置电压VNCS以控制NMOS电流源。 栅极偏置发生器包括参考电流发生器，以产生相对独立于电源电压变化的参考电流。 温度补偿器调节参考电流以提供温度补偿电流。 电流镜将温度补偿电流复制到偏置电压发生器。 偏置电压发生器产生偏置电压。