发明授权
US5942917A High speed ratioed CMOS logic structures for a pulsed input environment
失效
用于脉冲输入环境的高速比CMOS逻辑结构
- 专利标题： High speed ratioed CMOS logic structures for a pulsed input environment
- 专利标题（中）： 用于脉冲输入环境的高速比CMOS逻辑结构
-
申请号： US999102申请日： 1997-12-29
-
公开(公告)号： US5942917A公开(公告)日： 1999-08-24
- 发明人: Barbara A. Chappell , Terry I. Chappell , Mark S. Milshtein , Thomas D. Fletcher
- 申请人： Barbara A. Chappell , Terry I. Chappell , Mark S. Milshtein , Thomas D. Fletcher
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： H03K19/20
- IPC分类号： H03K19/20 ; H03K19/0948 ; H03K19/096 ; H03K19/094
摘要：
A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.
公开/授权文献
- US5266097A Aminoureaformaldehyde fertilizer method and composition 公开/授权日：1993-11-30
信息查询
IPC分类:
