- 专利标题: Error correction coding and decoding method, and circuit using said method
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申请号: US48954申请日: 1998-03-26
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公开(公告)号: US5951708A公开(公告)日: 1999-09-14
- 发明人: Hideo Yoshida
- 申请人: Hideo Yoshida
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX7-132461 19950530
- 主分类号: H03M13/00
- IPC分类号: H03M13/00 ; H03M13/15 ; H03M13/47 ; G11C29/00
摘要:
In the coding and decoding of Reed-Solomon codes formed of symbols larger than information symbols, redundant circuitry is eliminated, error detection and correction are preformed using a simple construction, and the reliability of error detection and correction is improved by processing only data of the same size as the information symbols. Two bits of dummy data which are surplus bits in 10 bits of one symbol of information are supplied from a dummy data input circuit to 8 bit input data. At the same time, syndrome data is generated form the surplus parts of check symbols by a syndrome data correction circuit. A part of the 10 bit data is selected by a selector, and supplied to a Galois field summation circuit. The output of the Galois field summation circuit is output to a register, and the output of this register is either selected without modification or via a Galois field coefficient multiplying circuit by a selector, and supplied to the Galois field summation circuit. The output of the register is output as syndrome data by a syndrome output terminal.
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