A process for fabricating electronic devices which includes the steps of providing a structure that includes a substrate with an overlying dielectric layer having one or more contact holes and/or vias formed therein; depositing a barrier layer over the structure so that the barrier layer penetrates into the contact holes and/or vias; plasma etching the deposited barrier layer so as to modify its surface morphology; and after modifying the surface morphology of the deposited barrier layer, depositing a metalization layer over the barrier layer. A two-step preclean to facet upper corners of the holes and/or vias and to clean bottoms of the holes and/or vias is performed prior to the deposition of the barrier layer.