发明授权
US5968160A Method and apparatus for processing data in multiple modes in accordance
with parallelism of program by using cache memory
失效
根据程序的并行性通过使用高速缓冲存储器来处理多种模式的数据的方法和装置
- 专利标题： Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
- 专利标题（中）： 根据程序的并行性通过使用高速缓冲存储器来处理多种模式的数据的方法和装置
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申请号： US923632申请日： 1997-09-04
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公开(公告)号： US5968160A公开(公告)日： 1999-10-19
- 发明人: Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
- 申请人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX2-237666 19900907; JPX2-247557 19900919
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06F9/318 ; G06F9/38 ; G06F12/08 ; G06F15/173 ; G06F15/80 ; G06F15/16
摘要：
A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.
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