The invention relates to an integrated circuit, containing an A/D converter and a test circuit, the latter in a test mode enabling explicit testing of analog and digital control signals of the circuit by supplying these control signals to circuit sections of the A/D converter and thus generating digital data signals at the output of the A/D converter. Analog signals, like bias signals and reference signals, can be selected and supplied to the input facility of the converter. Subsequently, a digital representation of the selected signal is obtained at the output facility of the converter. Digital signals, like clock signals, can be selected and supplied directly to the output facility. The output facility is operated by a clock signal and constructs a clocked version of the selected digital signal, which is subsequently available at the output. Thus, selected signals, either digital or analog, are available at the output of the converter and can be compared to specified data.