An arrangement for improving the operation of an analog to digital converter (A/D), which can form part of an integrated circuit, the A/D converter being coupled to a reference voltage and having a plurality of input pins associated therewith comprises: a resistor divider having a plurality of resistors coupled in series, the resistor divider having an upper node coupled to a source of voltage to be converted, having a lower node coupled to a source of reference potential and having a plurality of intermediate nodes; and, each of the upper intermediate nodes being coupled to a respective one of the input pins of the A/D converter. The A/D converter can have enhanced resolution and/or an extended dynamic range when the voltage level being tested is divided arid the reference voltage is reduced. A corresponding method comprises the steps of: successively scaling down a voltage to be converted to a series of stepped down voltage levels; applying the successively stepped down voltage levels to respective ones of the input pins; and, sequentially scanning and acquiring a plurality of scaled A/D converter values from the input pins.