SAR ADC capable of full-scale voltage auto-tuning and method for the same

    公开(公告)号:US12224765B1

    公开(公告)日:2025-02-11

    申请号:US18194172

    申请日:2023-03-31

    Abstract: An SAR ADC includes: at least one sub-ADC, configured to convert a corresponding input signal to a corresponding SAR code; and a tuning control unit, configured to adjust a full-scale voltage (VFS) of each of the sub-ADC to a corresponding predetermined target level in a VFS tuning mode. The tuning control unit generates a tuning code to control an adjusting capacitor array coupled to the sub-ADC for tuning the VFS. The tuning control unit controls the sub-ADC to convert plural reference voltages in the VFS tuning mode and extrapolating the conversion result to determine a corresponding calibrating VFS. The tuning control unit determines whether the calibrating VFS meeting the target VFS and loops the adjusting process in a linear search method or in a SAR method.

    Programmable gain amplifier and a delta sigma analog-to-digital converter containing the PGA

    公开(公告)号:US12199630B2

    公开(公告)日:2025-01-14

    申请号:US18061512

    申请日:2022-12-05

    Inventor: Jun Zhang

    Abstract: A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

    Analog-to-digital converter and analog-to-digital conversion method using the same

    公开(公告)号:US12191881B2

    公开(公告)日:2025-01-07

    申请号:US18150636

    申请日:2023-01-05

    Abstract: An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

    LOW-POWER DUAL DOWN-CONVERSION WI-FI WAKE-UP RECEIVER

    公开(公告)号:US20240422677A1

    公开(公告)日:2024-12-19

    申请号:US18815086

    申请日:2024-08-26

    Abstract: A Wi-Fi wake-up receiver that receives wake-up signals encoded using orthogonal frequency division multiplexing based on-off keying (OFDM-OOK) modulation includes receiver circuitry having analog envelope detector circuitry configured to non-linearly down-convert an input signal and provide an energy signal for sampling by an analog-to-digital converter (ADC). A wake-up signal for waking up a main radio in a Wi-Fi device can be based on the digitized energy signal. The receiver circuitry can further include, upstream of the envelope detector circuitry and the ADC in the signal chain, an analog mixer for linearly down-converting the input signal and a low-pass filter for attenuating adjacent-channel interferer (ACI) signals prior to the non-linear down-conversion by the envelope detector circuitry. Sampling of the energy signal rather than the higher-bandwidth input signal yield power savings in the ADC and associated circuitry such as a modem.

    Method and apparatus for monitoring nasal breathing

    公开(公告)号:US12160213B1

    公开(公告)日:2024-12-03

    申请号:US17820713

    申请日:2022-08-18

    Applicant: Apple Inc.

    Inventor: Ido Luft

    Abstract: This disclosure is directed to a nasal breathing monitoring system with an ultrasonic transducer (e.g., a microphone) to be placed on or near the outside of the user's nose and record an audio signal of the sound of the user's breathing. The recorded breathing audio signal may be digitized and analyzed, e.g., based on its spectral characteristics, in order to determine one or more breathing characteristics of the user's breathing. The system may then adjust some system parameter based on the determined one or more breathing characteristics, e.g., a signal gain, a filter, feedback to the user, etc. The system may also use the one or more breathing characteristics to: recognize a particular user, present a breathing exercise to a user, tailor particular user feedback, or compare the user's breathing characteristics to historical breathing data for the user and/or historical breathing data from other users obtained via an anonymized database.

    ADAPTIVE ANALOG PARTIAL SUM ACCUMULATION TECHNOLOGY FOR ENERGY-EFFICIENT COMPUTE-IN-MEMORY

    公开(公告)号:US20240396568A1

    公开(公告)日:2024-11-28

    申请号:US18792714

    申请日:2024-08-02

    Abstract: Systems, apparatuses and methods may provide for technology including a digital to analog conversion (DAC) stage to generate analog input activation signals, a multiply-accumulate (MAC) computation stage coupled to the DAC stage, the MAC computation stage to generate output activation results based on the analog input activation signals and multi-bit weight data stored in the MAC computation stage, an analog integration stage coupled to the MAC computation stage, the analog integration stage to conduct partial sum accumulations on the output activation results, and analog to digital conversion (ADC) stage coupled to the analog integration stage, the ADC stage to generate digital computation results based on an output of the analog integration stage, and a controller to vary a number of cycles in the partial sum accumulations based on an overflow condition associated with one or more of the output activation results or the output of the analog integration stage.

    DIGITAL CORRECTION METHOD FOR DYNAMIC RANGE EXPANSION OF MULTIPLE ADCS

    公开(公告)号:US20240396567A1

    公开(公告)日:2024-11-28

    申请号:US18635047

    申请日:2024-04-15

    Abstract: A digital correction method for dynamic range expansion of multiple ADCs includes: obtaining gain and offset correction values of other channels relative to a standard channel CH1 based on iterative computations through positive and negative amplitude auxiliary values and positive and negative base values, then performing gain-offset error correction on the other channels, and then calculating phase differences of the other channels relative to the standard channel CH1 and constructing fractional delay filters with a Farrow structure corresponding to the channels, correcting sampling data X2, . . . , XM after performing the gain-offset error correction. Digital correction of sampling data collected from multiple channels in a multi-ADC system is realized while ensuring that respective dynamic ranges of the sampling data with different gains output by the multiple channels are not lost.

    HYBRID DIGITAL AND ANALOG SIGNAL GENERATION SYSTEMS AND METHODS

    公开(公告)号:US20240219505A1

    公开(公告)日:2024-07-04

    申请号:US18601300

    申请日:2024-03-11

    Inventor: Houston Fortney

    Abstract: An analog signal generating source comprising two or more digital-to-analog converters (DAC) combined to generate one or more frequency components. The analog signal source comprises a first path for generating substantially low frequency signals, the first path comprising a first one of the DACs; and a second path for generating substantially high frequency signals, the second path comprising a second one of the DACs. The analog signal source also comprises a data processor for processing an input signal and providing the processed input signal to the first and second paths; a combining circuit configured to combine outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; and a servo loop configured to use the sensed source signal to adjust as need to maintain the source signal to substantially agree with the input signal.

    Relative adaptive encoding
    10.
    发明授权

    公开(公告)号:US11991490B2

    公开(公告)日:2024-05-21

    申请号:US17948114

    申请日:2022-09-19

    Applicant: Vutility, Inc.

    CPC classification number: H04Q9/00 G08C19/00 H03M1/0617

    Abstract: An electricity usage monitor may include a coupling component to couple the electricity usage monitor to monitor an electrical circuit, a meter to measure electricity usage of the electrical circuit, an encoder to receive, from the meter, an electricity usage measurement to generate a measurement transmission based on the electricity usage measurement, and a communication interface configured to receive the measurement transmission from the encoder and to transmit the measurement transmission into a communication network for communication to a destination on the communication network.

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